Marco Antonio Zanata Alves

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Philippe NavauxProfessor Informatics Institute, UFRGSVerified email at inf.ufrgs.br
Luigi CarroFull Professor, Instituto de InformaticaVerified email at inf.ufrgs.br
Matthias DienerResearch Scientist in Computer Science, University of IllinoisVerified email at illinois.edu
Francis Birck MoreiraPhDVerified email at inf.ufrgs.br
Eduardo Cunha de AlmeidaFederal University of ParanáVerified email at inf.ufpr.br
Antonio Carlos Schneider BeckUniversidade Federal do Rio Grande do SulVerified email at inf.ufrgs.br
Henrique Cota de FreitasAssociate Professor, PUC MinasVerified email at pucminas.br
João Paulo Cardoso de LimaTechnische Universität Dresden and ScaDS.AIVerified email at tu-dresden.de
Tiago R. KepePhD Student, Federal University of Paraná. and System Analyst, Federal Institute of ParanáVerified email at ifpr.edu.br
André GrégioAssistant Professor at UFPRVerified email at inf.ufpr.br
Rafael Fão de MouraEstudante de Doutorado acadêmico, Universidade Federal do Rio Grande do SulVerified email at inf.ufrgs.br
Marcus BotacinAssistant Professor @ Texas A&M UniversityVerified email at tamu.edu
Diego Gomes ToméPh.D. Student at CWIVerified email at cwi.nl
Geraldo F. OliveiraETH ZurichVerified email at inf.ethz.ch
Aline Santana CordeiroBsC Computer Science, Universidade Federal do ParanáVerified email at inf.ufpr.br
Israel KorenProfessor of Computer Engineering, University of MassachusettsVerified email at ecs.umass.edu
Carlos VillaviejaGoogleVerified email at google.com
Alexandre CarissimiUniversidade Federal do Rio Grande do SulVerified email at inf.ufrgs.br
Jean-Francois MehautUniversité de Grenoble AlpesVerified email at univ-grenoble-alpes.fr
Hameeza AhmedNED UniversityVerified email at neduet.edu.pk

Marco Antonio Zanata Alves

Federal University of Paraná (UFPR)

Verified email at inf.ufpr.br - Homepage

Computer Architecture Cache Memories Energy Efficiency Multicore Processors Smart Memories


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Operand size reconfiguration for big data processing in memory PC Santos, GF Oliveira, DG Tomé, MAZ Alves, EC Almeida, L Carro Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017	86	2017
Sinuca: A validated micro-architecture simulator MAZ Alves, C Villavieja, M Diener, FB Moreira, POA Navaux 2015 IEEE 17th International Conference on High Performance Computing and …, 2015	63	2015
Using memory access traces to map threads and data on hierarchical multi-core platforms EHM da Cruz, MAZ Alves, A Carissimi, POA Navaux, CP Ribeiro, ... 2011 IEEE International Symposium on Parallel and Distributed Processing …, 2011	59	2011
Affinity-based thread and data mapping in shared memory systems M Diener, EHM Cruz, MAZ Alves, POA Navaux, I Koren ACM Computing Surveys (CSUR) 49 (4), 1-38, 2016	54	2016
Evaluating thread placement based on memory access patterns for multi-core processors M Diener, F Madruga, E Rodrigues, M Alves, J Schneider, P Navaux, ... 2010 IEEE 12th International Conference on High Performance Computing and …, 2010	47	2010
Large vector extensions inside the HMC MAZ Alves, M Diener, PC Santos, L Carro 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016	46	2016
A compiler for automatic selection of suitable processing-in-memory instructions H Ahmed, PC Santos, JPC Lima, RF Moura, MAZ Alves, ACS Beck, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 564-569, 2019	45	2019
Nim: An hmc-based machine for neuron computation GF Oliveira, PC Santos, MAZ Alves, L Carro Applied Reconfigurable Computing: 13th International Symposium, ARC 2017 …, 2017	34	2017
Kernel-based thread and data mapping for improved memory affinity M Diener, EHM Cruz, MAZ Alves, POA Navaux, A Busse, HU Heiss IEEE Transactions on Parallel and Distributed Systems 27 (9), 2653-2666, 2015	34	2015
Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols EHM Cruz, M Diener, MAZ Alves, POA Navaux Journal of Parallel and Distributed Computing 74 (3), 2215-2228, 2014	32	2014
Database processing-in-memory: an experimental study TR Kepe, EC de Almeida, MAZ Alves Proceedings of the VLDB Endowment 13 (3), 334-347, 2019	26	2019
AntiViruses under the microscope: A hands-on perspective M Botacin, FD Domingues, F Ceschin, R Machnicki, MAZ Alves, ... Computers & Security 112, 102500, 2022	24	2022
Process mapping based on memory access traces EHM Cruz, MAZ Alves, POA Navaux 2010 11th Symposium on Computing Systems, 72-79, 2010	24	2010
HEAVEN: A Hardware-Enhanced AntiVirus ENgine to accelerate real-time, signature-based malware detection M Botacin, MZ Alves, D Oliveira, A Grégio Expert Systems with Applications 201, 117083, 2022	23	2022
A generic processing in memory cycle accurate simulator under hybrid memory cube architecture GF Oliveira, PC Santos, MAZ Alves, L Carro 2017 International Conference on Embedded Computer Systems: Architectures …, 2017	23	2017
Energy savings via dead sub-block prediction MAZ Alves, K Khubaib, E Ebrahimi, VT Narasiman, C Villavieja, ... Computer Architecture and High Performance Computing (SBAC-PAD), 2012 IEEE …, 2012	23	2012
Locality and balance for communication-aware thread mapping in multicore systems M Diener, EHM Cruz, MAZ Alves, MS Alhakeem, POA Navaux, HU Heiß Euro-Par 2015: Parallel Processing: 21st International Conference on …, 2015	22	2015
Investigation of shared l2 cache on many-core processors MAZ Alves, HC Freitas, POA Navaux 22th International Conference on Architecture of Computing Systems 2009, 1-10, 2009	22	2009
Processing in 3D memories to speed up operations on complex data structures PC Santos, GF Oliveira, JP Lima, MAZ Alves, L Carro, ACS Beck 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 897-900, 2018	21	2018
Impact of parallel workloads on NoC architecture design HC de Freitas, LM Schnorr, MAZ Alves, POA Navaux 2010 18th euromicro conference on parallel, distributed and network-based …, 2010	21	2010

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