Xavier Vera
Xavier Vera
Intel Labs Barcelona, Malardalens University, Universitat Politecnica de Catalunya, UNSW
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Cited by
Cited by
Penelope: The NBTI-aware processor
J Abella, X Vera, A Gonzalez
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
Data cache locking for higher program predictability
X Vera, B Lisper, J Xue
ACM SIGMETRICS Performance Evaluation Review 31 (1), 272-282, 2003
Impact of parameter variations on circuits and microarchitecture
OS Unsal, JW Tschanz, K Bowman, V De, X Vera, A Gonzalez, O Ergin
Ieee Micro 26 (6), 30-39, 2006
Architectures for online error detection and recovery in multicore processors
D Gizopoulos, M Psarakis, SV Adve, P Ramachandran, SKS Hari, D Sorin, ...
2011 Design, Automation & Test in Europe, 1-6, 2011
IATAC: a smart predictor to turn-off L2 cache lines
J Abella, A González, X Vera, MFP O'Boyle
ACM Transactions on Architecture and Code Optimization (TACO) 2 (1), 55-77, 2005
Low vccmin fault-tolerant cache with highly predictable performance
J Abella, J Carretero, P Chaparro, X Vera, A González
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
Data caches in multitasking hard real-time systems
X Vera, B Lisper, J Xue
RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003, 154-165, 2003
Let's study whole-program cache behaviour analytically
X Vera, J Xue
Proceedings Eighth International Symposium on High Performance Computer …, 2002
Enhancing reliability of a many-core processor
X Vera, O Unsal, O Ergin, J Abella, A González
US Patent 8,074,110, 2011
Data cache locking for tight timing calculations
X Vera, B Lisper, J Xue
ACM Transactions on Embedded Computing Systems (TECS) 7 (1), 1-38, 2007
Efficient and accurate analytical modeling of whole-program data cache behavior
J Xue, X Vera
IEEE Transactions on Computers 53 (5), 547-566, 2004
Exploiting narrow values for soft error tolerance
O Ergin, O Unsal, X Vera, A Gonzalez
IEEE Computer Architecture Letters 5 (2), 12-12, 2006
A fast and accurate framework to analyze and optimize cache memory behavior
X Vera, N Bermudo, J Llosa, A González
ACM Transactions on Programming Languages and Systems (TOPLAS) 26 (2), 263-300, 2004
Accelerating microprocessor silicon validation by exposing ISA diversity
N Foutris, D Gizopoulos, M Psarakis, X Vera, A Gonzalez
Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011
Selective replication: A lightweight technique for soft errors
X Vera, J Abella, J Carretero, A González
ACM Transactions on Computer Systems (TOCS) 27 (4), 1-30, 2010
Mt-sbst: Self-test optimization in multithreaded multicore architectures
N Foutris, M Psarakis, D Gizopoulos, A Apostolakis, X Vera, A González
2010 IEEE International Test Conference, 1-10, 2010
Disabling cache portions during low voltage operations
C Wilkerson, MM Khellah, V De, M Zhang, J Abella, JC Casado, ...
US Patent 8,103,830, 2012
Dynamically estimating lifetime of a semiconductor device
X Vera, J Abella, O Unsal, O Ergin, A González
US Patent 8,151,094, 2012
Electromigration for microarchitects
J Abella, X Vera
ACM Computing Surveys (CSUR) 42 (2), 1-18, 2010
Refueling: Preventing wire degradation due to electromigration
J Abella, X Vera, OS Unsal, O Ergin, A González, JW Tschanz
IEEE micro 28 (6), 37-46, 2008
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