| A predictor–corrector algorithm for fast polynomial chaos-based uncertainty quantification of multi-walled carbon nanotube interconnects Y Li, S Bhatnagar, A Merkely, DC Weber, S Roy IEEE Transactions on Components, Packaging and Manufacturing Technology 9 …, 2019 | 14 | 2019 |
| Variability-aware performance assessment of multi-walled carbon nanotube interconnects using a predictor-corrector polynomial chaos scheme S Bhatnagar, A Merkley, R Berdine, Y Li, S Roy 2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium …, 2018 | 5 | 2018 |
| Hierarchical polynomial chaos for variation analysis of silicon photonics microresonators X Cao, S Bhatnagar, M Nikdast, S Roy 2019 International Applied Computational Electromagnetics Society Symposium …, 2019 | 4 | 2019 |
| Modified D-Latch Enabled BEC1 Carry-Select Adder with Low Power-Delay Product and Area Efficiency S Bhatnagar, H Gupta, S Jain Proceedings of the International Conference on Recent Cognizance in Wireless …, 2016 | 1 | 2016 |
| Predictor-corrector algorithms and their scalability analysis for fast stochastic modeling of multi-walled carbon nanotube interconnects S Bhatnagar, Y Li, A Merkely, D Weber, S Roy 2019 Joint International Symposium on Electromagnetic Compatibility, Sapporo …, 2019 | | 2019 |
| Performance Assessment of Multi-Walled Carbon Nanotube Interconnects Using Advanced Polynomial Chaos Schemes S Bhatnagar Colorado State University, 2019 | | 2019 |
| Analysis of MOSFET density and reduction in power consumption of Carry Select Adder using gate diffusion input S Bhatnagar, V Agrawal, R Marwal 2016 International Conference on Recent Advances and Innovations in …, 2016 | | 2016 |
| REDUCTION IN AREA AND POWER ANALYSIS WITH D-LATCH ENABLED CARRY SELECT ADDER USING GATE DIFFUSION INPUT S BHATNAGAR, V AGRAWAL | | |
