Jaydeep Kulkarni
Jaydeep Kulkarni
UT Austin; imec; Intel; Purdue; IISc
Verified email at - Homepage
Cited by
Cited by
Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates
Q Cao, H Kim, N Pimparkar, JP Kulkarni, C Wang, M Shim, K Roy, ...
Nature 454 (7203), 495-500, 2008
A 160 mV robust Schmitt trigger based subthreshold SRAM
JP Kulkarni, K Kim, K Roy
IEEE Journal of Solid-State Circuits 42 (10), 2303-2313, 2007
Enabling the internet of things: From integrated circuits to integrated systems
M Alioto
Springer, 2017
Fundamentals of III-V semiconductor MOSFETs
S Oktyabrsky, DY Peide
Springer, 2010
Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design
JP Kulkarni, K Roy
IEEE transactions on very large scale integration (VLSI) systems 20 (2), 319-332, 2011
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design
V Saripalli, S Datta, V Narayanan, JP Kulkarni
2011 IEEE/ACM International Symposium on Nanoscale Architectures, 45-52, 2011
A 0.45–1 V fully-integrated distributed switched capacitor DC-DC converter with high density MIM capacitor in 22 nm tri-gate CMOS
R Jain, BM Geuskens, ST Kim, MM Khellah, J Kulkarni, JW Tschanz, V De
IEEE Journal of Solid-State Circuits 49 (4), 917-927, 2014
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
JP Kulkarni, K Kim, K Roy
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
16.2 eDRAM-CIM: Compute-in-memory design with reconfigurable embedded-dynamic-memory array realizing adaptive data converters and charge-domain computing
S Xie, C Ni, A Sayal, P Jain, F Hamzaoglu, JP Kulkarni
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 248-250, 2021
Postsilicon voltage guard-band reduction in a 22 nm graphics execution core using adaptive voltage scaling and dynamic power gating
M Cho, ST Kim, C Tokunaga, C Augustine, JP Kulkarni, K Ravichandran, ...
IEEE Journal of Solid-State Circuits 52 (1), 50-63, 2016
Enabling wide autonomous DVFS in a 22 nm graphics execution core using a digitally controlled fully integrated voltage regulator
ST Kim, YC Shih, K Mazumdar, R Jain, JF Ryan, C Tokunaga, ...
IEEE Journal of Solid-State Circuits 51 (1), 18-30, 2015
Process variation tolerant SRAM array for ultra low voltage applications
JP Kulkarni, K Kim, SP Park, K Roy
Proceedings of the 45th annual Design Automation Conference, 108-113, 2008
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
A Raychowdhury, B Geuskens, J Kulkarni, J Tschanz, K Bowman, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 352-353, 2010
Buried Power Rails and Back-side Power Grids: ArmŽ CPU Power Delivery Network Design Beyond 5nm
D. Prasad, S. S. Teja Nibhanupudi, S. Das, O. Zografos, B. Chehab, S. Sarkar ...
IEEE International Electron Device Meeting (IEDM), 2019
5.6 Mb/mm 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 …
JP Kulkarni, J Keane, KH Koo, S Nalam, Z Guo, E Karl, K Zhang
IEEE Journal of Solid-State Circuits 52 (1), 229-239, 2016
A 12.08-TOPS/W all-digital time-domain CNN engine using bi-directional memory delay lines for energy efficient edge computing
A Sayal, SST Nibhanupudi, S Fathima, JP Kulkarni
IEEE Journal of Solid-State Circuits 55 (1), 60-75, 2019
A read-disturb-free, differential sensing 1R/1W port, 8T bitcell array
JP Kulkarni, A Goel, P Ndai, K Roy
IEEE transactions on very large scale integration (VLSI) systems 19 (9 …, 2010
Capacitive-coupling wordline boosting with self-induced VCCcollapse for write VMINreduction in 22-nm 8T SRAM
J Kulkarni, B Geuskens, T Karnik, M Khellah, J Tschanz, V De
2012 IEEE International Solid-State Circuits Conference, 234-236, 2012
Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks
JP Kulkarni, BM Geuskens, J Tschanz, VK De, MM Khellah
US Patent 9,299,395, 2016
A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS
R Jain, B Geuskens, M Khellah, S Kim, J Kulkarni, J Tschanz, V De
2013 Symposium on VLSI Circuits, C174-C175, 2013
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