Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element GW Burr, RM Shelby, C di Nolfo, JW Jang, RS Shenoy, P Narayanan, ... Electron Devices Meeting (IEDM), 2014 IEEE International, 29.5. 1-29.5. 4, 2014 | 1147 | 2014 |
Optimization of Conductance Change in Pr1–xCaxMnO3-Based Synaptic Devices for Neuromorphic Systems JW Jang, S Park, GW Burr, H Hwang, YH Jeong IEEE Electron Device Letters 36 (5), 457-459, 2015 | 303 | 2015 |
Neuromorphic speech systems using advanced ReRAM-based synapse S Park, A Sheri, J Kim, J Noh, J Jang, M Jeon, B Lee, BR Lee, BH Lee, ... 2013 IEEE International Electron Devices Meeting, 25.6. 1-25.6. 4, 2013 | 206 | 2013 |
7.1 An 11.5 TOPS/W 1024-MAC butterfly structure dual-core sparsity-aware neural processing unit in 8nm flagship mobile SoC J Song, Y Cho, JS Park, JW Jang, S Lee, JH Song, JG Lee, I Kang 2019 IEEE international solid-state circuits conference-(ISSCC), 130-132, 2019 | 143 | 2019 |
Sparsity-aware and re-configurable NPU architecture for Samsung flagship mobile SoC JW Jang, S Lee, D Kim, H Park, AS Ardestani, Y Choi, C Kim, Y Kim, H Yu, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 106 | 2021 |
Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part I: Al/Mo/Pr0.7Ca0.3MnO3 Material Improvements and Device Measurements K Moon, A Fumarola, S Sidler, J Jang, P Narayanan, RM Shelby, GW Burr, ... IEEE Journal of the Electron Devices Society 6, 146-155, 2017 | 75 | 2017 |
ReRAM-based synaptic device for neuromorphic computing JW Jang, S Park, YH Jeong, H Hwang 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1054-1057, 2014 | 61 | 2014 |
Hardware implementation of associative memory characteristics with analogue-type resistive-switching device K Moon, S Park, J Jang, D Lee, J Woo, E Cha, S Lee, J Park, J Song, ... Nanotechnology 25 (49), 495204, 2014 | 57 | 2014 |
9.5 A 6K-MAC feature-map-sparsity-aware neural processing unit in 5nm flagship mobile SoC JS Park, JW Jang, H Lee, D Lee, S Lee, H Jung, S Lee, S Kwon, K Jeong, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 152-154, 2021 | 56 | 2021 |
Oxide based nanoscale analog synapse device for neural signal recognition system D Lee, J Park, K Moon, J Jang, S Park, M Chu, J Kim, J Noh, M Jeon, ... 2015 IEEE International Electron Devices Meeting (IEDM), 4.7. 1-4.7. 4, 2015 | 56 | 2015 |
Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Impact of conductance response S Sidler, I Boybat, RM Shelby, P Narayanan, J Jang, A Fumarola, K Moon, ... 2016 46th European Solid-State Device Research Conference (ESSDERC), 440-443, 2016 | 48 | 2016 |
A multi-mode 8k-mac hw-utilization-aware neural processing unit with a unified multi-precision datapath in 4-nm flagship mobile soc JS Park, C Park, S Kwon, T Jeon, Y Kang, H Lee, D Lee, J Kim, HS Kim, ... IEEE Journal of Solid-State Circuits 58 (1), 189-202, 2022 | 46 | 2022 |
Accelerating machine learning with non-volatile memory: Exploring device and circuit tradeoffs A Fumarola, P Narayanan, LL Sanches, S Sidler, J Jang, K Moon, ... 2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016 | 41 | 2016 |
Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part II: Impact of Al/Mo/Pr0.7Ca0.3MnO3 Device Characteristics on Neural Network … A Fumarola, S Sidler, K Moon, J Jang, RM Shelby, P Narayanan, ... IEEE Journal of the Electron Devices Society 6, 169-178, 2017 | 32 | 2017 |
ReRAM-based analog synapse and IMT neuron device for neuromorphic system K Moon, E Cha, D Lee, J Jang, J Park, H Hwang 2016 International Symposium on VLSI Technology, Systems and Application …, 2016 | 24 | 2016 |
Reducing circuit design complexity for neuromorphic machine learning systems based on non-volatile memory arrays P Narayanan, LL Sanches, A Fumarola, RM Shelby, S Ambrogio, J Jang, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 18 | 2017 |
Scalable neuron circuit using conductive-bridge RAM for pattern reconstructions JW Jang, B Attarimashalkoubeh, A Prakash, H Hwang, YH Jeong IEEE Transactions on Electron Devices 63 (6), 2610-2613, 2016 | 17 | 2016 |
Multilayer Perceptron Algorithm: Impact of Nonideal Conductance and Area-Efficient Peripheral Circuits LL Sanches, A Fumarola, S Sidler, P Narayanan, I Boybat, J Jang, ... Neuro-inspired Computing Using Resistive Synaptic Devices, 209-231, 2017 | 2 | 2017 |
Characterization of low frequency noise in nanowire FETs considering variability and quantum effects SH Lee, YR Kim, JH Hong, EY Jeong, JW Jang, JS Yoon, DW Kim, ... 71st Device Research Conference, 123-124, 2013 | 2 | 2013 |
Neural processor I Ovsiannikov, AS Ardestani, JH Hassoun, L Wang, SH Lee, S Joonho, ... US Patent 12,086,700, 2024 | 1 | 2024 |