| Gate-all-around nanowire MOSFET and method of formation K Cheng, BB Doris, P Hashemi, A Khakifirooz, A Reznicek US Patent 8,969,934, 2015 | 143 | 2015 |
| Integrated circuit having MOSFET with embedded stressor and method to fabricate same K Cheng, P Hashemi, A Khakifirooz, A Reznicek US Patent 8,975,697, 2015 | 136 | 2015 |
| High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET K Cheng, A Khakifirooz, N Loubet, S Luning, T Nagumo, M Vinet, Q Liu, ... 2012 International Electron Devices Meeting, 18.1. 1-18.1. 4, 2012 | 123 | 2012 |
| Nanowire transistor structures with merged source/drain regions using auxiliary pillars P Hashemi, A Khakifirooz, A Reznicek US Patent 9,257,527, 2016 | 98 | 2016 |
| Fabrication of nano-sheet transistors with different threshold voltages K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,653,289, 2017 | 77 | 2017 |
| Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub-10-nm nanowire diameter P Hashemi, L Gomez, JL Hoyt IEEE electron device letters 30 (4), 401-403, 2009 | 76 | 2009 |
| Demonstration of nanosecond operation in stochastic magnetic tunnel junctions C Safranski, J Kaiser, P Trouilloud, P Hashemi, G Hu, JZ Sun Nano letters 21 (5), 2040-2045, 2021 | 69 | 2021 |
| Vertical transistor with air gap spacers K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,443,982, 2016 | 64 | 2016 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 63 | 2016 |
| Enhanced hole transport in short-channel strained-SiGe p-MOSFETs L Gomez, P Hashemi, JL Hoyt IEEE transactions on electron devices 56 (11), 2644-2651, 2009 | 63 | 2009 |
| Channel-last replacement metal-gate vertical field effect transistor K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,525,064, 2016 | 60 | 2016 |
| Stacked complementary fets featuring vertically stacked horizontal nanowires K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,837,414, 2017 | 56 | 2017 |
| Ultrathin Strained-Ge Channel P-MOSFETs With High-/Metal Gate and Sub-1-nm Equivalent Oxide Thickness P Hashemi, W Chern, HS Lee, JT Teherani, Y Zhu, J Gonsalvez, ... IEEE electron device letters 33 (7), 943-945, 2012 | 56 | 2012 |
| Perfectly symmetric gate-all-around FET on suspended nanowire K Cheng, P Hashemi, A Khakifirooz, A Reznicek US Patent 9,853,166, 2017 | 54 | 2017 |
| Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,773,913, 2017 | 53 | 2017 |
| Advanced 3D monolithic hybrid CMOS with sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI fin pFETs V Deshpande, V Djara, E O'Connor, P Hashemi, K Balakrishnan, M Sousa, ... 2015 IEEE International Electron Devices Meeting (IEDM), 8.8. 1-8.8. 4, 2015 | 53 | 2015 |
| Replacement III-V or germanium nanowires by unilateral confined epitaxial growth K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,570,551, 2017 | 50 | 2017 |
| Contact formation to 3D monolithic stacked FinFETs K Cheng, P Hashemi, A Khakifirooz, A Reznicek US Patent 9,659,963, 2017 | 49 | 2017 |
| Strained FinFET by epitaxial stressor independent of gate pitch K Cheng, P Hashemi, A Khakifirooz, A Reznicek, CVVS Surisetty US Patent 9,647,113, 2017 | 49 | 2017 |
| Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS A Khakifirooz, K Cheng, T Nagumo, N Loubet, T Adam, A Reznicek, ... 2012 Symposium on VLSI technology (VLSIT), 117-118, 2012 | 49 | 2012 |
Ammar NayfehProfessor in Electrical Engineering Khalifa UniversityVerified email at ku.ac.ae
