| Timeloop: A Systematic Approach to DNN Accelerator Evaluation A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ... 2019 IEEE International Symposium on Performance Analysis of Systems and …, 2019 | 576* | 2019 |
| A compute-in-memory chip based on resistive random-access memory W Wan, R Kubendran, C Schaefer, SB Eryilmaz, W Zhang, D Wu, S Deiss, ... Nature 608 (7923), 504-512, 2022 | 490 | 2022 |
| Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 450 | 2019 |
| Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators X Yang, M Gao, Q Liu, J Setter, J Pu, A Nayak, S Bell, K Cao, H Ha, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 272 | 2020 |
| MAGNet: A Modular Accelerator Generator for Neural Networks R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 158* | 2019 |
| A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models W Wan, R Kubendran, SB Eryilmaz, W Zhang, Y Liao, D Wu, S Deiss, ... 2020 IEEE International Solid-State Circuits Conference (ISSCC), 498-500, 2020 | 128 | 2020 |
| A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... IEEE Journal of Solid-State Circuits (JSSC) 55 (4), 920-932, 2020 | 106 | 2020 |
| A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... 2019 Symposium on VLSI Circuits, C300-C301, 2019 | 71* | 2019 |
| CHIMERA: A 0.92 TOPS, 2.2 TOPS/W edge AI accelerator with 2 MByte on-chip foundry resistive RAM for efficient training and inference M Giordano, K Prabhu, K Koul, RM Radway, A Gural, R Doshi, ZF Khan, ... 2021 symposium on VLSI circuits, 1-2, 2021 | 60 | 2021 |
| SAPIENS: A 64-kb RRAM-based non-volatile associative memory for one-shot learning and inference at the edge H Li, WC Chen, A Levy, CH Wang, H Wang, PH Chen, W Wan, WS Khwa, ... IEEE Transactions on Electron Devices 68 (12), 6637-6643, 2021 | 57 | 2021 |
| CHIMERA: A 0.92-TOPS, 2.2-TOPS/W edge AI accelerator with 2-MByte on-chip foundry resistive RAM for efficient training and inference K Prabhu, A Gural, ZF Khan, RM Radway, M Giordano, K Koul, R Doshi, ... IEEE Journal of Solid-State Circuits 57 (4), 1013-1026, 2022 | 42 | 2022 |
| A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping for Energy-Efficient RRAM-Based In-Memory Computing W Wan, R Kubendran, B Gao, S Josbi, P Raina, H Wu, G Cauwenberghs, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 40 | 2020 |
| RADAR: A fast and energy-efficient programming technique for multiple bits-per-cell RRAM arrays BQ Le, A Levy, TF Wu, RM Radway, ER Hsieh, X Zheng, M Nelson, ... IEEE Transactions on Electron Devices 68 (9), 4397-4403, 2021 | 37 | 2021 |
| Creating an Agile Hardware Design Flow R Bahr, C Barrett, N Bhagdikar, A Carsello, R Daly, C Donovick, D Durst, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 32 | 2020 |
| Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a coarse-grained reconfigurable array for flexible acceleration of dense linear algebra A Carsello, K Feng, T Kong, K Koul, Q Liu, J Melchert, G Nyengele, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 28 | 2022 |
| Automating vitiligo skin lesion segmentation using convolutional neural networks M Low, V Huang, P Raina 2020 IEEE 17th International Symposium on Biomedical Imaging (ISBI), 1-4, 2020 | 28 | 2020 |
| One-shot learning with memory-augmented neural networks using a 64-kbit, 118 GOPS/W RRAM-based non-volatile associative memory H Li, WC Chen, A Levy, CH Wang, H Wang, PH Chen, W Wan, HSP Wong, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 25 | 2021 |
| Aha: An agile approach to the design of coarse-grained reconfigurable accelerators and compilers K Koul, J Melchert, K Sreedhar, L Truong, G Nyengele, K Zhang, Q Liu, ... ACM Transactions on Embedded Computing Systems 22 (2), 1-34, 2023 | 22 | 2023 |
| Simba: Scaling Deep-Learning Inference with Chiplet-Based Architecture YS Shao, J Cemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ... Communications of the ACM 64 (6), 107-116, 2021 | 21 | 2021 |
| Apex: A framework for automated processing element design space exploration using frequent subgraph analysis J Melchert, K Feng, C Donovick, R Daly, R Sharma, C Barrett, ... Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 14 | 2023 |
Srikanth TennetiSr. Applied Scientist, Amazon Web Services | Caltech
