Matthew Mattina
Matthew Mattina
ARM
Verified email at alumni.princeton.edu
Title
Cited by
Cited by
Year
On-chip interconnection architecture of the tile processor
D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ...
IEEE micro 27 (5), 15-31, 2007
9652007
Tile64-processor: A 64-core soc with mesh interconnect
S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
7372008
Computing in parallel processing environments
PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ...
US Patent 8,738,860, 2014
1742014
Last level cache (llc) performance of data mining workloads on a cmp-a case study of parallel bioinformatics workloads
A Jaleel, M Mattina, B Jacob
The Twelfth International Symposium on High-Performance Computer …, 2006
1622006
Tarantula: a vector extension to the alpha architecture
R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ...
Proceedings 29th Annual International Symposium on Computer Architecture …, 2002
1322002
Caching in multicore and multiprocessor architectures
A Agarwal, IR Bratt, M Mattina
US Patent 7,805,575, 2010
722010
Caching in multicore and multiprocessor architectures
A Agarwal, IR Bratt, M Mattina
US Patent 7,805,575, 2010
682010
Managing cache memory in a parallel processing environment
D Wentzlaff, M Mattina, A Agarwal
US Patent 7,882,307, 2011
622011
Managing memory access in a parallel processing environment
M Mattina, D Wentzlaff, A Agarwal
US Patent 7,805,577, 2010
552010
Flow control method and apparatus for single packet arrival on a bidirectional ring interconnect
M Mattina
US Patent 7,551,564, 2009
552009
High performance, scalable multi chip interconnect
CG Ramey, M Mattina
US Patent 9,424,228, 2016
452016
Apparatus and method for partitioning a shared cache of a chip multi-processor
M Mattina, A Juan-Hormigo, J Emer, R Matas-Navarro
US Patent 7,558,920, 2009
452009
Multiprocessor chip having bidirectional ring interconnect
G Chrysos, M Mattina, S Felix
US Patent App. 10/855,509, 2006
432006
Managing set associative cache memory according to entry type
D Wentzlaff, M Mattina, A Agarwal
US Patent 7,461,210, 2008
392008
Caching in multicore and multiprocessor architectures
A Agarwal, IR Bratt, M Mattina
US Patent 7,853,755, 2010
372010
Protocol for maintaining cache coherency in a CMP
M Mattina, GZ Chrysos
US Patent 8,209,490, 2012
362012
Scale-sim: Systolic cnn accelerator simulator
A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna
arXiv preprint arXiv:1811.02883, 2018
322018
Mapping memory in a parallel processing environment
D Wentzlaff, M Mattina, A Agarwal
US Patent 7,620,791, 2009
312009
Per-set relaxation of cache inclusion
R Rajwar, M Mattina
US Patent App. 11/313,114, 2007
272007
Euphrates: Algorithm-soc co-design for low-power mobile continuous vision
Y Zhu, A Samajdar, M Mattina, P Whatmough
arXiv preprint arXiv:1803.11232, 2018
252018
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