| On-chip interconnection architecture of the tile processor D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ... IEEE micro 27 (5), 15-31, 2007 | 1185 | 2007 |
| Tile64-processor: A 64-core soc with mesh interconnect S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 847 | 2008 |
| Federated learning based on dynamic regularization DAE Acar, Y Zhao, RM Navarro, M Mattina, PN Whatmough, V Saligrama arXiv preprint arXiv:2111.04263, 2021 | 407 | 2021 |
| Computing in parallel processing environments PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ... US Patent 8,738,860, 2014 | 347 | 2014 |
| Scale-sim: Systolic cnn accelerator simulator A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna arXiv preprint arXiv:1811.02883, 2018 | 314 | 2018 |
| Last level cache (llc) performance of data mining workloads on a cmp-a case study of parallel bioinformatics workloads A Jaleel, M Mattina, B Jacob The Twelfth International Symposium on High-Performance Computer …, 2006 | 177 | 2006 |
| Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers C Banbury, C Zhou, I Fedorov, R Matas, U Thakker, D Gope, ... Proceedings of Machine Learning and Systems 3, 517-532, 2021 | 171 | 2021 |
| Tarantula: A vector extension to the alpha architecture R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ... ACM SIGARCH Computer Architecture News 30 (2), 281-292, 2002 | 145 | 2002 |
| Sparse: Sparse architecture search for cnns on resource-constrained microcontrollers I Fedorov, RP Adams, M Mattina, P Whatmough Advances in Neural Information Processing Systems 32, 2019 | 135 | 2019 |
| A systematic methodology for characterizing scalability of dnn accelerators using scale-sim A Samajdar, JM Joseph, Y Zhu, P Whatmough, M Mattina, T Krishna 2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020 | 106 | 2020 |
| Caching in multicore and multiprocessor architectures A Agarwal, IR Bratt, M Mattina US Patent 7,805,575, 2010 | 99 | 2010 |
| High performance, scalable multi chip interconnect CG Ramey, M Mattina US Patent 9,424,228, 2016 | 98 | 2016 |
| Euphrates: Algorithm-soc co-design for low-power mobile continuous vision Y Zhu, A Samajdar, M Mattina, P Whatmough arXiv preprint arXiv:1803.11232, 2018 | 97 | 2018 |
| Caching in multicore and multiprocessor architectures A Agarwal, IR Bratt, M Mattina US Patent 7,805,575, 2010 | 93 | 2010 |
| Managing cache memory in a parallel processing environment D Wentzlaff, M Mattina, A Agarwal US Patent 7,882,307, 2011 | 78 | 2011 |
| TinyLSTMs: Efficient neural speech enhancement for hearing aids I Fedorov, M Stamenovic, C Jensen, LC Yang, A Mandell, Y Gan, ... arXiv preprint arXiv:2005.11138, 2020 | 74 | 2020 |
| Fixynn: Efficient hardware for mobile computer vision via transfer learning PN Whatmough, C Zhou, P Hansen, SK Venkataramanaiah, J Seo, ... arXiv preprint arXiv:1902.11128, 2019 | 61 | 2019 |
| Flow control method and apparatus for single packet arrival on a bidirectional ring interconnect M Mattina US Patent 7,551,564, 2009 | 60 | 2009 |
| Managing memory access in a parallel processing environment M Mattina, D Wentzlaff, A Agarwal US Patent 7,805,577, 2010 | 57 | 2010 |
| Systolic tensor array: An efficient structured-sparse GEMM accelerator for mobile CNN inference ZG Liu, PN Whatmough, M Mattina IEEE Computer Architecture Letters 19 (1), 34-37, 2020 | 56 | 2020 |
Paul N WhatmoughQualcomm AI Research, Harvard UniversityVerified email at qti.qualcomm.com
