| The gem5 simulator N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... ACM SIGARCH Computer Architecture News 39 (2), 1-7, 2011 | 6190 | 2011 |
| Efficient virtual memory for big memory servers A Basu, J Gandhi, J Chang, MD Hill, MM Swift Proceedings of the 40th Annual International Symposium on Computer …, 2013 | 429 | 2013 |
| Heterogeneous system coherence for integrated CPU-GPU systems J Power, A Basu, J Gu, S Puthoor, BM Beckmann, MD Hill, SK Reinhardt, ... Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 213 | 2013 |
| Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks J Gandhi, A Basu, MD Hill, MM Swift Proceedings of the 47th Annual IEEE/ACM International Symposium on …, 2014 | 137 | 2014 |
| Observations and opportunities in architecting shared virtual memory for heterogeneous systems J Vesely, A Basu, M Oskin, GH Loh, A Bhattacharjee 2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016 | 120 | 2016 |
| Faastlane: Accelerating function-as-a-service workflows S Kotni, A Nayak, V Ganapathy, A Basu 2021 USENIX Annual Technical Conference (USENIX ATC 21). USENIX Association …, 2021 | 118 | 2021 |
| Reducing memory reference energy with opportunistic virtual caching A Basu, MD Hill, MM Swift Proceedings of the 39th International Symposium on Computer Architecture …, 2012 | 113 | 2012 |
| Scavenger: A new last level cache architecture with global block priority A Basu, N Kirman, M Kirman, M Chaudhuri, J Martinez 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007 | 87 | 2007 |
| The Gem5 Simulator. SIGARCH Comput. Archit. News 39, 2 (Aug. 2011), 1–7 N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... | 82 | 2011 |
| Scheduling Page Table Walks for Irregular GPU Applications S Shin, G Cox, M Oskin, GH Loh, Y Solihin, A Bhattacharjee, A Basu 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 70 | 2018 |
| Avoiding TLB Shootdowns through Self-invalidating TLB Entries A Awad, A Basu, S Blagodurov, Y Solihin, GH Loh 2017 26th International Conference on Parallel Architectures and Compilation …, 2017 | 57 | 2017 |
| BadgerTrap: a tool to instrument x86-64 TLB misses J Gandhi, A Basu, MD Hill, MM Swift ACM SIGARCH Computer Architecture News 42 (2), 20-23, 2014 | 52 | 2014 |
| Adaptive extension of leases for entries in a translation lookaside buffer A Awad, S Blagodurov, A Basu, MH Oskin, GH Loh, AG Kegel, DS Christie, ... US Patent 10,261,916, 2019 | 51* | 2019 |
| Karma: scalable deterministic record-replay A Basu, J Bobba, MD Hill International Conference on Supercomputing, 2011 | 51 | 2011 |
| Generic system calls for GPUs J Vesely, A Basu, A Bhattacharjee, GH Loh, M Oskin, SK Reinhardt 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 40 | 2018 |
| Multi-processor apparatus and method of detection and acceleration of lagging tasks A Basu, D Yudanov, DA Roberts, MR Meswani, S Blagodurov US Patent 10,592,279, 2020 | 39 | 2020 |
| Generic system calls for GPUs J Veselý, A Basu, A Bhattacharjee, GH Loh, M Oskin, SK Reinhardt 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 39 | 2018 |
| Neighborhood-aware address translation for irregular GPU applications S Shin, M LeBeane, Y Solihin, A Basu 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 36 | 2018 |
| Region based cache replacement policy utilizing usage information BM Beckmann, A Basu, SK Reinhardt US Patent App. 13/173,441, 2011 | 31 | 2011 |
| Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors VSS Ram, A Panwar, A Basu MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 26 | 2021 |
Mark D. HillUniversity of Wisconsin-Madison Professor EmeritusVerified email at cs.wisc.edu
