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Muzaffar Rao
Muzaffar Rao
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Title
Cited by
Cited by
Year
Defence against black hole and selective forwarding attacks for medical WSNs in the IoT
A Mathur, T Newe, M Rao
Sensors 16 (1), 118, 2016
932016
A secure end-to-end IoT solution
A Mathur, T Newe, W Elgenaidi, M Rao, G Dooly, D Toal
Sensors and Actuators A: Physical 263, 291-299, 2017
432017
Efficient hardware implementations and hardware performance evaluation of SHA-3 finalists
K Latif, MM Rao, A Aziz, A Mahboob
The Third SHA-3 Candidate Conference, 2012
402012
Secure hash algorithm-3 (SHA-3) implementation on Xilinx FPGAs, suitable for IoT applications
M Rao, T Newe, I Grout
International Journal on Smart Sensing and Intelligent Systems 7 (5), 1-6, 2014
372014
A study of network intrusion detection systems using artificial intelligence/machine learning
P Vanin, T Newe, LL Dhirani, E O’Connell, D O’Shea, B Lee, M Rao
Applied Sciences 12 (22), 11752, 2022
332022
AES implementation on Xilinx FPGAs suitable for FPGA based WBSNs
M Rao, T Newe, I Grout
2015 9th International Conference on Sensing Technology (ICST), 773-778, 2015
232015
Real-time video latency measurement between a robot and its remote control station: Causes and mitigation
A Kaknjo, M Rao, E Omerdic, L Robinson, D Toal, T Newe
Wireless Communications and Mobile Computing 2018, 1-19, 2018
182018
An FPGA based reconfigurable IPSec ESP core suitable for IoT applications
M Rao, J Coleman, T Newe
2016 10th International Conference on Sensing Technology (ICST), 1-5, 2016
162016
Healthcare WSN: cluster elections and selective forwarding defense
A Mathur, T Newe, M Rao
2015 9th International Conference on Next Generation Mobile Applications …, 2015
152015
Integration of autonomous intelligent vehicles into manufacturing environments: Challenges
L Lynch, F McGuinness, J Clifford, M Rao, J Walsh, D Toal, T Newe
Procedia Manufacturing 38, 1683-1690, 2019
142019
High speed implementation of a SHA-3 core on Virtex-5 and Virtex-6 FPGAs
M Rao, T Newe, I Grout, A Mathur
Journal of Circuits, Systems and Computers 25 (07), 1650069, 2016
132016
Efficient and high speed fpga bump in the wire implementation for data integrity and confidentiality services in the iot
T Newe, M Rao, D Toal, G Dooly, E Omerdic, A Mathur
Sensors for everyday life: Healthcare settings, 259-285, 2017
122017
Novel arithmetic architecture for high performance implementation of SHA-3 finalist KECCAK on FPGA platforms
K Latif, MM Rao, A Mahboob, A Aziz
Reconfigurable Computing: Architectures, Tools and Applications: 8th …, 2012
122012
An FPGA‐based reconfigurable IPSec AH core with efficient implementation of SHA‐3 for high speed IoT applications
M Rao, T Newe, I Grout, A Mathur
Security and Communication Networks 9 (16), 3282-3295, 2016
112016
FPGA based reconfigurable IPSec AH core suitable for IoT applications
M Rao, T Newe, I Grout, E Lewis, A Mathur
2015 IEEE International Conference on Computer and Information Technology …, 2015
102015
Zero-trust model for smart manufacturing industry
B Paul, M Rao
Applied Sciences 13 (1), 221, 2022
82022
Dynamical Phenomena at Interfaces, Surfaces and Membranes
M Wortis, U Seifert, K Berndl, B Fourcade, L Miao, M Rao, RKP Zia
Dynamical Phenomena at Interfaces, Surfaces and Membranes, 221, 1993
81993
An efficient high speed AES implementation using Traditional FPGA and LabVIEW FPGA platforms
M Rao, A Kaknjo, E Omerdic, D Toal, T Newe
2018 International Conference on Cyber-Enabled Distributed Computing and …, 2018
72018
Bump in the wire (BITW) security solution for a marine ROV remote control application
M Rao, T Newe, E Omerdic, A Kaknjo, W Elgenaidi, A Mathur, G Dooly, ...
Journal of information security and applications 38, 111-121, 2018
52018
An efficient implementation of FPGA based high speed IPSec (AH/ESP) core
M Rao, T Newe, E Omerdic, G Dooly, E Lewis, D Toal
International Journal of Internet Protocol Technology 11 (2), 97-109, 2018
52018
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