| A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking A Santiccioli, M Mercandelli, L Bertulessi, A Parisi, D Cherniak, AL Lacaita, ... IEEE Journal of Solid-State Circuits 55 (12), 3349-3361, 2020 | 76 | 2020 |
| A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter M Mercandelli, A Santiccioli, A Parisi, L Bertulessi, D Cherniak, AL Lacaita, ... IEEE Journal of Solid-State Circuits, 2021 | 68 | 2021 |
| A background calibration technique to control the bandwidth of digital PLLs M Mercandelli, L Grimaldi, L Bertulessi, C Samori, AL Lacaita, ... IEEE Journal of Solid-State Circuits 53 (11), 3243-3255, 2018 | 51 | 2018 |
| A 1.6-to-3.0-GHz Fractional- MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power A Santiccioli, M Mercandelli, AL Lacaita, C Samori, S Levantino IEEE Journal of Solid-State Circuits 54 (11), 3149-3160, 2019 | 37 | 2019 |
| A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power A Santiccioli, M Mercandelli, AL Lacaita, C Samori, S Levantino IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 1-4, 2019 | 37 | 2019 |
| A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs L Avallone, M Mercandelli, A Santiccioli, MP Kennedy, S Levantino, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (7), 2775-2786, 2021 | 24 | 2021 |
| 32.3 A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter M Mercandelli, A Santiccioli, SM Dartizio, A Shehata, F Tesolin, S Karman, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 445-447, 2021 | 14 | 2021 |
| A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping SM Dartizio, F Tesolin, M Mercandelli, A Santiccioli, A Shehata, S Karman, ... IEEE Journal of Solid-State Circuits 57 (6), 1723-1735, 2021 | 11 | 2021 |
| 32.8 A 98.4 fs-Jitter 12.9-to-15.1 GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays A Santiccioli, M Mercandelli, SM Dartizio, F Tesolin, S Karman, A Shehata, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 456-458, 2021 | 10 | 2021 |
| A 18.9-22.3 GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability S Karman, F Tesolin, A Dago, M Mercandelli, C Samori, S Levantino 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 67-70, 2021 | 8 | 2021 |
| Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise L Bertulessi, D Cherniak, M Mercandelli, C Samori, AL Lacaita, ... IEEE Transactions on Circuits and Systems I: Regular Papers 69 (5), 1858-1870, 2022 | 5 | 2022 |
| A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations G Bè, A Parisi, L Bertulessi, L Ricci, L Scaletti, M Mercandelli, AL Lacaita, ... IEEE Transactions on Circuits and Systems II: Express Briefs 69 (9), 3645-3649, 2022 | 4 | 2022 |
| Radar signal modulator with bandwidth compensation and frequency offset sequence D Cherniak, S Levantino, M Mercandelli US Patent 11,454,715, 2022 | 3 | 2022 |
| A digital PLL with multitap LMS-based bandwidth control M Mercandelli, L Bertulessi, C Samori, S Levantino IEEE Solid-State Circuits Letters 5, 126-129, 2022 | 3 | 2022 |
| A 3.7-to-4.1 GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter M Mercandelli, L Bertulessi, C Samori, S Levantino 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021 | 2 | 2021 |
| A 250-Mb/s Direct Phase Modulator With− 42.4-dB EVM Based on a 14-GHz Digital PLL D Cherniak, M Mercandelli, L Bertulessi, F Padovan, L Grimaldi, ... IEEE Solid-State Circuits Letters 3, 126-129, 2020 | 2 | 2020 |
| A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters L Scaletti, G Bè, A Parisi, L Bertulessi, L Ricci, M Mercandelli, S Levantino, ... 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), 20-24, 2022 | 1 | 2022 |
| Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators A Parisi, F Tesolin, M Mercandelli, L Bertulessi, AL Lacaita IEEE Microwave and Wireless Components Letters 31 (9), 1075-1078, 2021 | 1 | 2021 |
| A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter G Be, M Mercandelli, L Bertulessi SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on …, 2021 | | 2021 |
| A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity A Parisi, M Mercandelli, C Samori, AL Lacaita 2021 28th IEEE International Conference on Electronics, Circuits, and …, 2021 | | 2021 |
Salvatore LevantinoPolitecnico di MilanoVerified email at polimi.it
