Guodong Yin
Guodong Yin
Verified email at
Cited by
Cited by
A comprehensive model for ferroelectric FET capturing the key behaviors: Scalability, variation, stochasticity, and accumulation
S Deng, G Yin, W Chakraborty, S Dutta, S Datta, X Li, K Ni
2020 IEEE symposium on VLSI technology, 1-2, 2020
Enabling lower-power charge-domain nonvolatile in-memory computing with ferroelectric FETs
G Yin, Y Cai, J Wu, Z Duan, Z Zhu, Y Liu, Y Wang, H Yang, X Li
IEEE Transactions on Circuits and Systems II: Express Briefs 68 (7), 2262-2266, 2021
Yoloc: deploy large-scale neural network by rom-based computing-in-memory using residual branch on a chip
Y Chen, G Yin, Z Tan, M Lee, Z Yang, Y Liu, H Yang, K Ma, X Li
Proceedings of the 59th ACM/IEEE Design Automation Conference, 1093-1098, 2022
CapCAM: A multilevel capacitive content addressable memory for high-accuracy and high-scalability search and compute applications
X Ma, H Zhong, N Xiu, Y Chen, G Yin, V Narayanan, Y Liu, K Ni, H Yang, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (11 …, 2022
Capacitive content-addressable memory: A highly reliable and scalable approach to energy-efficient parallel pattern matching applications
N Xiu, Y Chen, G Yin, X Ma, H Yang, S George, X Li
Proceedings of the 2021 on Great Lakes Symposium on VLSI, 479-484, 2021
SAMBA: Single-ADC multi-bit accumulation compute-in-memory using nonlinearity-compensated fully parallel analog adder tree
Y Chen, G Yin, M Zhou, W Tang, Z Yang, M Lee, X Du, J Yue, J Liu, ...
IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
Hidden-ROM: A compute-in-ROM architecture to deploy large-scale neural networks on chip with flexible and scalable post-fabrication task transfer capability
Y Chen, G Yin, M Lee, W Tang, Z Yang, Y Liu, H Yang, X Li
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022
A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface
G Yin, M Zhou, Y Chen, W Tang, Z Yang, M Lee, X Du, J Yue, J Liu, ...
arXiv preprint arXiv:2212.04320, 2022
A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM
G Yin, Y Chen, M Lee, X Du, Y Ke, W Tang, Z Chen, M Zhou, J Yue, ...
2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024
ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns
Y Chen, G Yin, H Zhong, M Lee, H Yang, S George, V Narayanan, X Li
2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 153-158, 2024
Compute-in-memory devices, neural network accelerators, and electronic devices
X Li, G Yin, Y Chen, L Cheong, L Tianyu, W Tang, LEE Mingyen, DU Xirui, ...
US Patent App. 18/342,917, 2024
Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm Density in 65-nm …
G Yin, Y Chen, M Zhou, W Tang, M Lee, Z Yang, T Liao, X Du, ...
IEEE Journal of Solid-State Circuits, 2023
GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph
Y Chen, G Dai, M Zhou, M Lee, N Challapalle, G Yin, Z Yang, Y Liu, ...
arXiv preprint arXiv:2208.08600, 2022
The system can't perform the operation now. Try again later.
Articles 1–13