| Efficient processing of deep neural networks: A tutorial and survey V Sze, YH Chen, TJ Yang, JS Emer Proceedings of the IEEE 105 (12), 2295-2329, 2017 | 3622 | 2017 |
| Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks YH Chen, T Krishna, JS Emer, V Sze IEEE journal of solid-state circuits 52 (1), 127-138, 2016 | 3300 | 2016 |
| Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks YH Chen, J Emer, V Sze ACM SIGARCH computer architecture news 44 (3), 367-379, 2016 | 1678 | 2016 |
| A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor SS Mukherjee, C Weaver, J Emer, SK Reinhardt, T Austin Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003 | 1259 | 2003 |
| Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor DM Tullsen, SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm Proceedings of the 23rd annual international symposium on Computer …, 1996 | 1224 | 1996 |
| SCNN: An accelerator for compressed-sparse convolutional neural networks A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ... ACM SIGARCH computer architecture news 45 (2), 27-40, 2017 | 1212 | 2017 |
| Adaptive insertion policies for high performance caching MK Qureshi, A Jaleel, YN Patt, SC Steely, J Emer ACM SIGARCH Computer Architecture News 35 (2), 381-391, 2007 | 948 | 2007 |
| High performance cache replacement using re-reference interval prediction (RRIP) A Jaleel, KB Theobald, SC Steely Jr, J Emer ACM SIGARCH computer architecture news 38 (3), 60-71, 2010 | 922 | 2010 |
| Eyeriss v2: A flexible accelerator for emerging deep neural networks on mobile devices YH Chen, TJ Yang, J Emer, V Sze IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (2 …, 2019 | 792 | 2019 |
| Simultaneous multithreading: A platform for next-generation processors SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm, DM Tullsen IEEE micro 17 (5), 12-19, 1997 | 709 | 1997 |
| The soft error problem: An architectural perspective SS Mukherjee, J Emer, SK Reinhardt 11th International Symposium on High-Performance Computer Architecture, 243-247, 2005 | 578 | 2005 |
| Memory dependence prediction using store sets GZ Chrysos, JS Emer ACM SIGARCH Computer Architecture News 26 (3), 142-153, 1998 | 467 | 1998 |
| Understanding error propagation in deep learning neural network (DNN) accelerators and applications G Li, SKS Hari, M Sullivan, T Tsai, K Pattabiraman, J Emer, SW Keckler Proceedings of the International Conference for High Performance Computing …, 2017 | 456 | 2017 |
| Scheduling heterogeneous multi-cores through performance impact estimation (PIE) K Van Craeynest, A Jaleel, L Eeckhout, P Narvaez, J Emer ACM SIGARCH Computer Architecture News 40 (3), 213-224, 2012 | 436 | 2012 |
| Adaptive insertion policies for managing shared caches A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer Proceedings of the 17th international conference on Parallel architectures …, 2008 | 419 | 2008 |
| Techniques to reduce the soft error rate of a high-performance microprocessor C Weaver, J Emer, SS Mukherjee, SK Reinhardt ACM SIGARCH Computer Architecture News 32 (2), 264, 2004 | 383 | 2004 |
| Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading JL Lo, JS Emer, HM Levy, RL Stamm, DM Tullsen, SJ Eggers ACM Transactions on Computer Systems (TOCS) 15 (3), 322-354, 1997 | 370 | 1997 |
| Hardware for machine learning: Challenges and opportunities V Sze, YH Chen, J Emer, A Suleiman, Z Zhang 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2017 | 367 | 2017 |
| DAWG: A defense against cache timing attacks in speculative execution processors V Kiriansky, I Lebedev, S Amarasinghe, S Devadas, J Emer 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 326 | 2018 |
| Asim: A performance model framework J Emer, P Ahuja, E Borch, A Klauser, CK Luk, S Manne, SS Mukherjee, ... Computer 35 (2), 68-76, 2002 | 318 | 2002 |
Vivienne SzeAssociate Professor, EECS at MITVerified email at mit.edu
