Shang-Chun Lu
Cited by
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Surface passivation of Cu (In, Ga) Se2 using atomic layer deposited Al2O3
WW Hsu, JY Chen, TH Cheng, SC Lu, WS Ho, YY Chen, YJ Chien, ...
Applied Physics Letters 100 (2), 2012
Electronic structures of defects and magnetic impurities in MoS2 monolayers
SC Lu, JP Leburton
Nanoscale research letters 9, 1-9, 2014
Mobility enhancement of strained Si by optimized SiGe/Si/SiGe structures
SH Huang, TM Lu, SC Lu, CH Lee, CW Liu, DC Tsui
Applied Physics Letters 101 (4), 2012
Novel vertical hetero-and homo-junction tunnel field-effect transistors based on multi-layer 2D crystals
SC Lu, M Mohamed, W Zhu
2D Materials 3 (1), 011010, 2016
Superior performance of 5-nm gate length GaN nanowire nFET for digital logic applications
Y Chu, SC Lu, N Chowdhury, M Povolotskyi, G Klimeck, M Mohamed, ...
IEEE Electron Device Letters 40 (6), 874-877, 2019
First-principles study of Ge dangling bonds with different oxygen backbonds at Ge/GeO2 interface
HC Chang, SC Lu, TP Chou, CM Lin, CW Liu
Journal of Applied Physics 111 (7), 2012
First-Principles Study of GeO2/Ge Interfacial Traps and Oxide Defects
SC Lu, HC Chang, TP Chou, C Liu
2012 International Silicon-Germanium Technology and Device Meeting (ISTDM), 1-2, 2012
AB initio study and design of 2D materials/III-nitrides-based post-CMOS devices using first-principles multiphysics simulation framework
University of Illinois at Urbana-Champaign, 2019
Vertical hetero-and homo-junction tunnel field-effect transistors
W Zhu, SC Lu, M Mohamed
US Patent 10,236,386, 2019
Design Guidelines and Limitations of Multilayer Two-dimensional Vertical Tunneling FETs for UltraLow Power Logic Applications
SC Lu, Y Chu, Y Kim, MY Mohamed, G Klimeck, T Palacios, U Ravaioli
2018 International Conference on Simulation of Semiconductor Processes and …, 2018
Modeling of black phosphorus vertical TFETs without chemical doping for drain
SC Lu, Y Kim, MJ Gilbert, U Ravaioli, MY Mohamed
2017 International Conference on Simulation of Semiconductor Processes and …, 2017
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