| 3D-MAPS: 3D massively parallel processor with stacked memory DH Kim, K Athikulwongse, M Healy, M Hossain, M Jung, I Khorosh, ... Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 …, 2012 | 397* | 2012 |
| A study of through-silicon-via impact on the 3D stacked IC layout DH Kim, K Athikulwongse, SK Lim Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 344 | 2009 |
| TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC M Jung, J Mitra, DZ Pan, SK Lim Communications of the ACM 57 (1), 107-115, 2014 | 234 | 2014 |
| Design and CAD methodologies for low power gate-level monolithic 3D ICs SA Panth, K Samadi, Y Du, SK Lim Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 206* | 2014 |
| Edge separability-based circuit clustering with application to multilevel circuit partitioning J Cong, SK Lim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 194* | 2004 |
| Multiobjective microarchitectural floorplanning for 2-D and 3-D ICs M Healy, M Vittes, M Ekpanyapong, CS Ballapuram, SK Lim, HHS Lee, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 185* | 2006 |
| TSV stress aware timing analysis with applications to 3D-IC layout optimization J Yang, K Athikulwongse, YJ Lee, SK Lim, DZ Pan Proceedings of the 47th Design Automation Conference, 803-806, 2010 | 163* | 2010 |
| Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs X Zhao, J Minz, SK Lim IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (2 …, 2010 | 158* | 2010 |
| Thermal characterization of interlayer microfluidic cooling of three-dimensional integrated circuits with nonuniform heat flux YJ Kim, YK Joshi, AG Fedorov, YJ Lee, SK Lim | 146 | 2010 |
| Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system M Cho, C Liu, DH Kim, SK Lim, S Mukhopadhyay 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 694-697, 2010 | 145* | 2010 |
| Architecture, chip, and package co-design flow for 2.5 D IC design enabling heterogeneous IP reuse J Kim, G Murali, H Park, E Qin, H Kwon, V Chaitanya, K Chekuri, N Dasari, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 143* | 2019 |
| 3D floorplanning with thermal vias E Wong, SK Lim Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 139 | 2006 |
| Stress-driven 3D-IC placement with TSV keep-out zone and regularity study K Athikulwongse, A Chakraborty, JS Yang, DZ Pan, SK Lim 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 669-674, 2010 | 131 | 2010 |
| A design tradeoff study with monolithic 3D integration C Liu, SK Lim Thirteenth International Symposium on Quality Electronic Design (ISQED), 529-536, 2012 | 129 | 2012 |
| Physical design for 3D system on package SK Lim IEEE Design & Test of Computers 22 (6), 532-539, 2005 | 128 | 2005 |
| Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC C Liu, T Song, J Cho, J Kim, J Kim, SK Lim Proceedings of the 48th Design Automation Conference, 783-788, 2011 | 125 | 2011 |
| Pre-bond testable low-power clock tree design for 3D stacked ICs X Zhao, DL Lewis, HHS Lee, SK Lim Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 120* | 2009 |
| VLSI placement parameter optimization using deep reinforcement learning A Agnesina, K Chang, SK Lim Proceedings of the 39th international conference on computer-aided design, 1-9, 2020 | 108 | 2020 |
| Multiway partitioning with pairwise movement J Cong, SK Lim Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 105 | 1998 |
| Large scale circuit partitioning with loose/stable net removal and signal flow based clustering SK Lim, D Xu, J Cong, P Li, T Shibuya 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997 | 105 | 1997 |
Dae Hyun KimWashington State UniversityVerified email at eecs.wsu.edu
