Sparsity-aware and re-configurable NPU architecture for Samsung flagship mobile SoC JW Jang, S Lee, D Kim, H Park, AS Ardestani, Y Choi, C Kim, Y Kim, H Yu, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 106 | 2021 |
9.5 A 6K-MAC feature-map-sparsity-aware neural processing unit in 5nm flagship mobile SoC JS Park, JW Jang, H Lee, D Lee, S Lee, H Jung, S Lee, S Kwon, K Jeong, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 152-154, 2021 | 56 | 2021 |
A multi-mode 8k-mac hw-utilization-aware neural processing unit with a unified multi-precision datapath in 4-nm flagship mobile soc JS Park, C Park, S Kwon, T Jeon, Y Kang, H Lee, D Lee, J Kim, HS Kim, ... IEEE Journal of Solid-State Circuits 58 (1), 189-202, 2022 | 46 | 2022 |
ComPEND: Computation Pruning through Early Negative Detection for ReLU in a deep neural network accelerator D Lee, S Kang, K Choi Proceedings of the 2018 International Conference on Supercomputing, 139-148, 2018 | 35 | 2018 |
Deflection routing in 3D network-on-chip with TSV serialization J Lee, D Lee, S Kim, K Choi 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 29-34, 2013 | 16 | 2013 |
Energy-efficient partitioning of hybrid caches in multi-core architecture D Lee, K Choi VLSI-SoC: Internet of Things Foundations: 22nd IFIP WG 10.5/IEEE …, 2015 | 11 | 2015 |
Deflection routing in 3D network-on-chip with limited vertical bandwidth J Lee, D Lee, S Kim, K Choi ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (4 …, 2013 | 10 | 2013 |
ComPreEND: Computation pruning through predictive early negative detection for ReLU in a deep neural network accelerator N Kim, H Park, D Lee, S Kang, J Lee, K Choi IEEE Transactions on Computers 71 (7), 1537-1550, 2021 | 9 | 2021 |
Samsung neural processing unit: An ai accelerator and sdk for flagship mobile ap JS Park, H Lee, D Lee, J Moon, S Kwon, SH Ha, MS Kim, J Park, J Bang, ... 2021 IEEE Hot Chips 33 Symposium (HCS), 1-21, 2021 | 6 | 2021 |
A memetic quantum-inspired evolutionary algorithm for circuit bipartitioning problem D Lee, J Ahn, K Choi 2012 International SoC Design Conference (ISOCC), 159-162, 2012 | 5 | 2012 |
Dirty-block tracking in a direct-mapped DRAM cache with self-balancing dispatch D Lee, S Lee, S Ryu, K Choi ACM Transactions on Architecture and Code Optimization (TACO) 14 (2), 1-25, 2017 | 3 | 2017 |
Performance Enhancement of Systems using Emerging Memory Technologies 이동우 서울대학교 대학원, 2018 | | 2018 |