| CACTI 7: New tools for interconnect exploration in innovative off-chip memories R Balasubramonian, AB Kahng, N Muralimanohar, A Shafiee, V Srinivas ACM Transactions on Architecture and Code Optimization (TACO) 14 (2), 1-25, 2017 | 474 | 2017 |
| Systems and methods for testing packaged dies T Kazi, J Gemar, V Srinivas, V Mohan US Patent 7,075,175, 2006 | 119 | 2006 |
| CACTI-IO: CACTI with off-chip power-area-timing models NP Jouppi, AB Kahng, N Muralimanohar, V Srinivas Proceedings of the International Conference on Computer-Aided Design, 294-301, 2012 | 90 | 2012 |
| Cross-layer co-optimization of network design and chiplet placement in 2.5-D systems A Coskun, F Eris, A Joshi, AB Kahng, Y Ma, A Narayan, V Srinivas IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 44 | 2020 |
| Adaptive tuning of photonic devices in a photonic NoC through dynamic workload allocation JL Abellán, AK Coskun, A Gu, W Jin, A Joshi, AB Kahng, J Klamkin, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 39 | 2016 |
| Low-power clocking for a high-speed memory interface D West, V Srinivas, M Brunolli, J Suh US Patent 10,169,262, 2019 | 26 | 2019 |
| A cross-layer methodology for design and optimization of networks in 2.5 D systems A Coskun, F Eris, A Joshi, AB Kahng, Y Ma, V Srinivas 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 25 | 2018 |
| Metal-insulator-metal capacitor structures R Jakushokas, V Srinivas, RWC Kim US Patent 9,041,148, 2015 | 21 | 2015 |
| Low voltage differential signaling driver with programmable on-chip resistor termination AS Dixit, V Srinivas US Patent 8,008,944, 2011 | 21 | 2011 |
| Mobile system considerations for SDRAM interface trends AB Kahng, V Srinivas International Workshop on System Level Interconnect Prediction, 1-8, 2011 | 21 | 2011 |
| Digital output driver and input buffer using thin-oxide field effect transistors V Srinivas, V Mohan US Patent 7,605,618, 2009 | 15 | 2009 |
| SPROUT—Smart power routing tool for board-level exploration and prototyping R Bairamkulov, A Roy, M Nagarajan, V Srinivas, EG Friedman IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 14 | 2021 |
| Power delivery exploration methodology based on constrained optimization R Bairamkulov, K Xu, M Popovich, JS Ochoa, V Srinivas, EG Friedman IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 13 | 2019 |
| Learning-based prediction of package power delivery network quality Y Cao, AB Kahng, J Li, A Roy, V Srinivas, B Xu Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 13 | 2019 |
| Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems AK Coskun, A Gu, W Jin, A Joshi, AB Kahng, J Klamkin, Y Ma, J Recchio, ... 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 13 | 2016 |
| System design technology co-optimization for 3D integration at< 5nm nodes SC Song, G Nallapati, I Khan, N Nikfar, B Yan, M Miranda, B Lim, ... 2021 IEEE International Electron Devices Meeting (IEDM), 22.3. 1-22.3. 4, 2021 | 12 | 2021 |
| Metal-insulator-metal capacitor structures R Jakushokas, V Srinivas, RWC Kim US Patent 9,312,326, 2016 | 12 | 2016 |
| Dynamic control of signaling power based on an error rate DT Chun, V Srinivas, DI West, DV Sriramagiri, J Suh, J Thurston US Patent 9,633,698, 2017 | 11 | 2017 |
| Dynamic random access memory (DRAM) backchannel communication systems and methods DI West, MJ Brunolli, DT Chun, V Srinivas US Patent 9,881,656, 2018 | 10 | 2018 |
| High signal level compliant input/output circuits V Shankar, A Gupta, V Srinivas, V Mohan US Patent 8,593,203, 2013 | 9 | 2013 |
