Young H. Cho
Young H. Cho
Research Assistant Professor of CS/EE
Verified email at - Homepage
Cited by
Cited by
Reconfigurable computing: the theory and practice of FPGA-based computation
S Hauck, A DeHon
Morgan Kaufmann Pub, 2008
Specialized hardware for deep network packet filtering
YH Cho, S Navab, WH Mangione-Smith
International Conference on Field Programmable Logic and Applications, 452-461, 2002
Deep packet filter with dedicated logic and read only memories
YH Cho, WH Mangione-Smith
12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines …, 2004
A pattern matching co-processor for network security
YH Cho, WH Mangione-Smith
Proceedings. 42nd Design Automation Conference, 2005., 234-239, 2005
High-performance context-free parser for polymorphic malware detection
YH Cho, WH Mangione-Smith
US Patent App. 11/918,592, 2009
Fast reconfiguring deep packet filter for 1+ gigabit network
YH Cho, WH Mangione-Smith
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines …, 2005
Method and Apparatus for Deep Packet Inspection
W Mangione-Smith, YH Cho
US Patent App. 11/574,878, 2008
Deep network packet filter design for reconfigurable devices
YH Cho, WH Mangione-Smith
ACM Transactions on Embedded Computing Systems (TECS) 7 (2), 1-26, 2008
Efficient PMU networking with software defined networks
A Goodney, S Kumar, A Ravi, YH Cho
2013 IEEE International Conference on Smart Grid Communications …, 2013
On the interaction of clocks, power, and synchronization in duty-cycled embedded sensor nodes
T Schmid, R Shea, Z Charbiwala, J Friedman, MB Srivastava, HC Young
ACM Transactions on Sensor Networks 7 (3), 24.1-24.19, 2010
Exploiting manufacturing variations for compensating environment-induced clock drift in time synchronization
T Schmid, Z Charbiwala, J Friedman, YH Cho, MB Srivastava
ACM SIGMETRICS Performance Evaluation Review 36 (1), 97-108, 2008
Programmable hardware for deep packet filtering on a large signature set
YH Cho, WH Mangione-Smith
First Watson Conference on Interaction between Architecture, Circuits, and …, 2004
Toward quality of information aware rate control for sensor networks
ZM Charbiwala, S Zahedi, Y Kim, YH Cho, MB Srivastava
Fourth International Workshop on Feedback Control Implemenation and Design …, 2009
Reconfigurable Computing The Theory and Practice of FPGA-Based Computing
A Dehon, S Hauck
Elsevier, 2008
Angle-of-arrival assisted radio interferometry (ARI) target localization
J Friedman, Z Charbiwala, T Schmid, Y Cho, M Srivastava
MILCOM 2008-2008 IEEE Military Communications Conference, 1-7, 2008
Low-power high-accuracy timing systems for efficient duty cycling
T Schmid, J Friedman, Z Charbiwala, YH Cho, MB Srivastava
Proceedings of the 2008 international symposium on Low Power Electronics …, 2008
A thermal management and profiling method for reconfigurable hardware applications
PH Jones, JW Lockwood, YH Cho
2006 International Conference on Field Programmable Logic and Applications, 1-7, 2006
Reconfigurable content-based router using hardware-accelerated language parser
J Moscola, JW Lockwood, YH Cho
ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (2 …, 2008
Programmable hardware for deep packet filtering
YH Cho, WH Mangione-Smith
US Patent 7,519,995, 2009
Streaming hierarchical clustering for concept mining
M Looks, A Levine, GA Covington, RP Loui, JW Lockwood, YH Cho
2007 IEEE Aerospace Conference, 1-12, 2007
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