| Bandwidth-constrained mapping of cores onto NoC architectures S Murali, G De Micheli Proceedings design, automation and test in Europe conference and exhibition …, 2004 | 839 | 2004 |
| NoC synthesis flow for customized domain specific multiprocessor systems-on-chip D Bertozzi, A Jalabert, S Murali, R Tamhankar, S Stergiou, L Benini, ... IEEE transactions on parallel and distributed systems 16 (2), 113-129, 2005 | 704 | 2005 |
| Analysis of error recovery schemes for networks on chips S Murali, T Theocharides, N Vijaykrishnan, MJ Irwin, L Benini, ... IEEE Design & Test of Computers 22 (5), 434-442, 2005 | 390 | 2005 |
| SUNMAP: a tool for automatic topology selection and generation for NoCs S Murali, G De Micheli Proceedings of the 41st annual Design Automation Conference, 914-919, 2004 | 387 | 2004 |
| xpipesCompiler: A tool for instantiating application-specific Networks on Chip A Jalabert, S Murali, L Benini, G De Micheli Design, Automation, and Test in Europe, 157-171, 2008 | 354 | 2008 |
| Networks on chips L Benini, G De Micheli, TT Ye Morgan Kaufmann, 2006 | 327 | 2006 |
| Designing application-specific networks on chips with floorplan information S Murali, P Meloni, F Angiolini, D Atienza, S Carta, L Benini, G De Micheli, ... 2006 IEEE/ACM International Conference on Computer Aided Design, 355-362, 2006 | 234 | 2006 |
| A methodology for mapping multiple use-cases onto networks on chips S Murali, M Coenen, A Radulescu, K Goossens, G De Micheli Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 200 | 2006 |
| Network-on-chip design and synthesis outlook D Atienza, F Angiolini, S Murali, A Pullini, L Benini, G De Micheli Integration 41 (3), 340-359, 2008 | 167 | 2008 |
| SunFloor 3D: A tool for networks on chip topology synthesis for 3-D systems on chips C Seiculescu, S Murali, L Benini, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 154 | 2010 |
| Temperature-aware processor frequency assignment for MPSoCs using convex optimization S Murali, A Mutapcic, D Atienza, R Gupta, S Boyd, G De Micheli Proceedings of the 5th IEEE/ACM international conference on Hardware …, 2007 | 154 | 2007 |
| Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees S Murali, L Benini, G De Micheli Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 148 | 2005 |
| Temperature control of high-performance multi-core platforms using convex optimization S Murali, A Mutapcic, D Atienza, R Gupta, S Boyd, L Benini, G De Micheli Proceedings of the conference on Design, automation and test in Europe, 110-115, 2008 | 125 | 2008 |
| Synthesis of networks on chips for 3D systems on chips S Murali, C Seiculescu, L Benini, G De Micheli 2009 Asia and South Pacific Design Automation Conference, 242-247, 2009 | 121 | 2009 |
| Mapping and configuration methods for multi-use-case networks on chips S Murali, M Coenen, A Radulescu, K Goossens, G De Micheli Asia and South Pacific Conference on Design Automation, 2006., 6 pp., 2006 | 113 | 2006 |
| A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip S Murali, D Atienza, L Benini, G De Micheli 2006 43rd ACM/IEEE Design Automation Conference, 845-848, 2006 | 99 | 2006 |
| A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control M Coenen, S Murali, A Ruadulescu, K Goossens, G De Micheli Proceedings of the 4th international conference on Hardware/software …, 2006 | 97 | 2006 |
| Bringing NoCs to 65 nm A Pullini, F Angiolini, S Murali, D Atienza, G De Micheli, L Benini IEEE Micro 27 (5), 75-85, 2007 | 95 | 2007 |
| Method to design network-on-chip (NOC)-based communication systems S Murali, L Benini, G De Micheli US Patent 8,042,087, 2011 | 91 | 2011 |
| An application-specific design methodology for STbus crossbar generation S Murali, G De Micheli Design, Automation and Test in Europe, 1176-1181, 2005 | 89 | 2005 |
