Baris Taskin
Baris Taskin
Professor of ECE, Drexel University
Verified email at - Homepage
Cited by
Cited by
Timing optimization through clock skew scheduling
IS Kourtev, B Taskin, EG Friedman
Springer US, 2009
Improving line-based QCA memory cell design through dual phase clocking
B Taskin, B Hong
IEEE transactions on very large scale integration (VLSI) systems 16 (12 …, 2008
Delay insertion method in clock skew scheduling
B Taskin, IS Kourtev
Proceedings of the 2005 international symposium on Physical design, 47-54, 2005
Design methodology for voltage-scaled clock distribution networks
C Sitik, W Liu, B Taskin, E Salman
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016
Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation
S Nilakantan, K Sangaiah, A More, G Salvadory, B Taskin, M Hempstead
2015 IEEE International Symposium on Performance Analysis of Systems and …, 2015
Timing-driven physical design for VLSI circuits using resonant rotary clocking
B Taskin, J Wood, IS Kourtev
2006 49th IEEE International Midwest Symposium on Circuits and Systems 1 …, 2006
FinFET-based low-swing clocking
C Sitik, E Salman, L Filippini, SJ Yoon, B Taskin
ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (2), 1-20, 2015
A shift-register-based QCA memory architecture
B Taskin, A Chiu, J Salkind, D Venutolo
ACM Journal on Emerging Technologies in Computing Systems (JETC) 5 (1), 1-18, 2009
TSV antennas for multi-band wireless communication
V Pano, I Tekin, I Yilmaz, Y Liu, KR Dandekar, B Taskin
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 10 (1 …, 2020
Innovative propagation mechanism for inter-chip and intra-chip communication
Y Liu, V Pano, D Patron, K Dandekar, B Taskin
2015 IEEE 16th Annual Wireless and Microwave Technology Conference (WAMICON …, 2015
Post-CTS clock skew scheduling with limited delay buffering
J Lu, B Taskin
2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 224-227, 2009
Dual-phase line-based QCA memory design
B Taskin, B Hong
2006 Sixth IEEE Conference on Nanotechnology 1, 302-305, 2006
Clock mesh synthesis with gated local trees and activity driven register clustering
J Lu, X Mao, B Taskin
Proceedings of the International Conference on Computer-Aided Design, 691-697, 2012
From RTL to GDSII: An ASIC design course development using SynopsysŪ University Program
J Lu, B Taskin
2011 IEEE International Conference on Microelectronic Systems Education, 72-75, 2011
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing
J Lu, V Honkote, X Chen, B Taskin
2011 Design, Automation & Test in Europe, 1-6, 2011
CROA: Design and analysis of the custom rotary oscillatory array
V Honkote, B Taskin
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (10 …, 2010
Custom topology rotary clock router with tree subnetworks
B Taskin, J Demaio, O Farell, M Hazeltine, R Ketner
ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (3 …, 2009
Synchrotrace: Synchronization-aware architecture-agnostic traces for lightweight multicore simulation of cmp and hpc workloads
K Sangaiah, M Lui, R Jagtap, S Diestelhorst, S Nilakantan, A More, ...
ACM Transactions on Architecture and Code Optimization (TACO) 15 (1), 1-26, 2018
Clock buffer polarity assignment considering capacitive load
J Lu, B Taskin
2010 11th International Symposium on Quality Electronic Design (ISQED), 765-770, 2010
Interconnects for dna, quantum, in-memory, and optical computing: Insights from a panel discussion
A Ganguly, S Abadal, I Thakkar, NE Jerger, M Riedel, M Babaie, ...
IEEE micro 42 (3), 40-49, 2022
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