Machine learning for electronic design automation: A survey G Huang, J Hu, Y He, J Liu, M Ma, Z Shen, J Wu, Y Xu, H Zhang, K Zhong, ... ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (5 …, 2021 | 202 | 2021 |

14.3 A 65nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy … J Yue, Z Yuan, X Feng, Y He, Z Zhang, X Si, R Liu, MF Chang, X Li, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2020 | 125 | 2020 |

15.2 A 2.75-to-75.9 TOPS/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong CIM with simultaneous computation and weight updating J Yue, X Feng, Y He, Y Huang, Y Wang, Z Yuan, M Zhan, J Liu, JW Su, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 238-240, 2021 | 115 | 2021 |

STICKER-IM: A 65 nm computing-in-memory NN processor using block-wise sparsity optimization and inter/intra-macro data reuse J Yue, Y Liu, Z Yuan, X Feng, Y He, W Sun, Z Zhang, X Si, R Liu, Z Wang, ... IEEE Journal of Solid-State Circuits 57 (8), 2560-2573, 2022 | 24 | 2022 |

A 28nm 16.9-300TOPS/W computing-in-memory processor supporting floating-point NN inference/training with intensive-CIM sparse-digital architecture J Yue, C He, Z Wang, Z Cong, Y He, M Zhou, W Sun, X Li, C Dou, F Zhang, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 1-3, 2023 | 22 | 2023 |

An RRAM-based digital computing-in-memory macro with dynamic voltage sense amplifier and sparse-aware approximate adder tree Y He, J Yue, X Feng, Y Huang, H Jia, J Wang, L Zhang, W Sun, H Yang, ... IEEE Transactions on Circuits and Systems II: Express Briefs 70 (2), 416-420, 2022 | 10 | 2022 |

Mixed‐Precision Continual Learning Based on Computational Resistance Random Access Memory Y Li, W Zhang, X Xu, Y He, D Dong, N Jiang, F Wang, Z Guo, S Wang, ... Advanced Intelligent Systems 4 (8), 2200026, 2022 | 10 | 2022 |

7.3 a 28nm 38-to-102-TOPS/W 8b multiply-less approximate digital SRAM compute-in-memory macro for neural-network inference Y He, H Diao, C Tang, W Jia, X Tang, Y Wang, J Yue, X Li, H Yang, H Jia, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 130-132, 2023 | 9 | 2023 |

C-rram: A fully input parallel charge-domain rram-based computing-in-memory design with high tolerance for rram variations Y He, Y Huang, J Yue, W Sun, L Zhang, Y Liu 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 3279-3283, 2022 | 6 | 2022 |

Accuracy optimization with the framework of non-volatile computing-in-memory systems Y Huang, Y He, J Yue, H Yang, Y Liu IEEE Transactions on Circuits and Systems I: Regular Papers 69 (2), 518-529, 2021 | 5 | 2021 |

A 5.6-89.9 TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro J Yue, M Zhan, Z Wang, Y He, Y Li, S Yu, W Sun, L Jie, C Dou, X Li, N Sun, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 4 | 2023 |

A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference S Yu, Y He, H Jia, W Sun, M Zhou, L Lei, W Zhao, G Ma, H Yang, Y Liu IEEE Transactions on Circuits and Systems II: Express Briefs, 2023 | 4 | 2023 |

Bit-aware fault-tolerant hybrid retraining and remapping schemes for RRAM-based computing-in-memory systems Y Huang, Y He, J Wang, J Yue, L Zhang, K Zou, H Yang, Y Liu IEEE Transactions on Circuits and Systems II: Express Briefs 69 (7), 3144-3148, 2022 | 4 | 2022 |

Block-circulant neural network accelerator featuring fine-grained frequency-domain quantization and reconfigurable FFT modules Y He, J Yue, Y Liu, H Yang 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 813-818, 2021 | 4 | 2021 |

Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC Y Huang, Y He, J Yue, W Sun, H Yang, Y Liu 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 684-689, 2022 | 3 | 2022 |

Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array L Zhang, D Mu, Y Huang, J Wang, Y He, Y Li, L Liu, K Zou, H Yang, Y Liu IEEE Transactions on Circuits and Systems II: Express Briefs 70 (3), 1124-1128, 2022 | 2 | 2022 |

34.7 A 28nm 2.4Mb/mm^{2} 6.9 - 16.3TOPS/mm^{2} eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and RefreshingY He, S Fan, X Li, L Lei, W Jia, C Tang, Y Li, Z Huang, Z Du, J Yue, X Li, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 578-580, 2024 | 1 | 2024 |

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update J Yue, Y Liu, X Feng, Y He, J Wang, Z Yuan, M Zhan, J Liu, JW Su, ... IEEE Journal of Solid-State Circuits, 2023 | 1 | 2023 |

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design C He, Z Wang, F Xiang, Z Dai, Y He, J Yue, Y Liu IEEE Transactions on Circuits and Systems II: Express Briefs, 2023 | 1 | 2023 |

A Heterogeneous Microprocessor for Intermittent AI Inference using Nonvolatile-SRAM-based Compute-In-Memory T Wu, L Lei, Y He, W Jia, S Yu, Y Huang, H Jia, H Yang, Y Liu IEEE Transactions on Circuits and Systems II: Express Briefs, 2023 | 1 | 2023 |