| Memory system optimization for FPGA-based implementation of quasi-cyclic LDPC codes decoders X Chen, J Kang, S Lin, V Akella IEEE Transactions on Circuits and Systems I: Regular Papers 58 (1), 98-111, 2010 | 113 | 2010 |
| High-throughput efficient non-binary LDPC decoder based on the simplified min-sum algorithm X Chen, CL Wang IEEE Transactions on Circuits and Systems I: Regular Papers 59 (11), 2784-2794, 2012 | 75 | 2012 |
| A simplified min-sum decoding algorithm for non-binary LDPC codes CL Wang, X Chen, Z Li, S Yang IEEE Transactions on Communications 61 (1), 24-32, 2012 | 67 | 2012 |
| QSN—A simple circular-shift network for reconfigurable quasi-cyclic LDPC decoders X Chen, S Lin, V Akella IEEE Transactions on Circuits and Systems II: Express Briefs 57 (10), 782-786, 2010 | 66 | 2010 |
| Efficient configurable decoder architecture for nonbinary quasi-cyclic LDPC codes X Chen, S Lin, V Akella IEEE Transactions on Circuits and Systems I: Regular Papers 59 (1), 188-197, 2011 | 39 | 2011 |
| Detection and handling of unbalanced errors in interleaved codewords S Jeon, X Chen US Patent 9,092,350, 2015 | 24 | 2015 |
| Hardware implementation of a backtracking-based reconfigurable decoder for lowering the error floor of quasi-cyclic LDPC codes X Chen, J Kang, S Lin, V Akella IEEE Transactions on Circuits and Systems I: Regular Papers 58 (12), 2931-2943, 2011 | 24 | 2011 |
| Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing X Chen, J Kang, S Lin, V Akella 2009 Design, Automation & Test in Europe Conference & Exhibition, 1530-1535, 2009 | 24 | 2009 |
| FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes X Chen, Q Huang, S Lin, V Akella 2009 47th Annual Allerton Conference on Communication, Control, and …, 2009 | 22 | 2009 |
| Method and system for determining soft information offsets X Chen, J Kang, J Zhu, YY Tai US Patent 9,647,697, 2017 | 18 | 2017 |
| Read threshold adjustment with feedback information from error recovery X Chen, W Wang, J Yuan, JL Whaley US Patent 10,468,117, 2019 | 11 | 2019 |
| Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA X Chen, V Akella ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4 (4), 1-17, 2011 | 11 | 2011 |
| Method and apparatus for adaptive data retention management in non-volatile memory J Yuan, JL Whaley, X Chen, W Wang US Patent 10,839,886, 2020 | 9 | 2020 |
| Dynamic multi-stage decoding J Tao, C Niang-Chu, MJ Dancho, X Chen US Patent 10,558,522, 2020 | 9 | 2020 |
| Error recovery of cross-die logical pages in a solid state device X Chen US Patent 10,732,899, 2020 | 5 | 2020 |
| Syndrome layered decoding for LDPC codes X Chen, J Zhu, YY Tai US Patent 9,136,877, 2015 | 5 | 2015 |
| Adaptive LLR based on syndrome weight S Jeon, Y Tai, J Zhu, X Chen US Patent 9,009,576, 2015 | 5 | 2015 |
| Compressing data from multiple reads for error control management in memory systems X Chen, YY Tai, J Zhu, S Jeon US Patent 9,239,751, 2016 | 4 | 2016 |
| Universal and reconfigurable QC-LDPC encoder J Zhu, YY Tai, X Chen US Patent 9,236,886, 2016 | 4 | 2016 |
| Dynamic multi-stage decoding J Tao, C Niang-Chu, MJ Dancho, X Chen US Patent 11,093,326, 2021 | 1 | 2021 |
