Derek Chiou
Derek Chiou
Partner Architect, Microsoft and Adjunct Associate Professor and Research Scientist, UT Austin
Verified email at ece.utexas.edu
Title
Cited by
Cited by
Year
A reconfigurable fabric for accelerating large-scale datacenter services
A Putnam, AM Caulfield, ES Chung, D Chiou, K Constantinides, J Demme, ...
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
9562014
A cloud-scale acceleration architecture
AM Caulfield, ES Chung, A Putnam, H Angepat, J Fowers, M Haselman, ...
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
3742016
Fpga-accelerated simulation technologies (fast): Fast, full-system, cycle-accurate simulators
D Chiou, D Sunwoo, J Kim, NA Patil, W Reinhart, DE Johnson, J Keefe, ...
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
2072007
RAMP: Research accelerator for multiple processors
J Wawrzynek, D Patterson, M Oskin, SL Lu, C Kozyrakis, JC Hoe, D Chiou, ...
IEEE micro 27 (2), 46-57, 2007
2012007
Azure accelerated networking: SmartNICs in the public cloud
D Firestone, A Putnam, S Mundkur, D Chiou, A Dabagh, M Andrewartha, ...
15th {USENIX} Symposium on Networked Systems Design and Implementation …, 2018
1972018
Application-specific memory management for embedded systems using software-controlled caches
D Chiou, P Jain, L Rudolph, S Devadas
Proceedings of the 37th Annual Design Automation Conference, 416-419, 2000
1472000
GPGPU performance and power estimation using machine learning
G Wu, JL Greathouse, A Lyashevsky, N Jayasena, D Chiou
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
1392015
Serving dnns in real time at datacenter scale with project brainwave
E Chung, J Fowers, K Ovtcharov, M Papamichael, A Caulfield, ...
IEEE Micro 38 (2), 8-20, 2018
1282018
Dynamic Cache Partitioning via Columnization
D Chiou, S Devadas, L Rudolph, BS Ang
119*1999
Method and apparatus for curious and column caching
D Chiou, BS Ang
US Patent 6,370,622, 2002
1082002
A framework for packet selection and reporting
N Duffield, D Chiou, B Claise, A Greenberg, Grossglauser, M, J Rexford
1052009
START-NG: Delivering Seamless Parallel Computing
D Chiou, BS Ang, R Greiner, Arvind, JC Hoe, MJ Beckerle, JE Hicks, ...
Proceedings of EURO-PAR’95, 101-116, 1995
981995
Performance studies of the Monsoon dataflow processor
J Hicks, D Chiou, BS Ang, Arvind
Journal of Parallel and Distributed Computing 18 (3), 273-300, 1993
97*1993
An fpga-based in-line accelerator for memcached
M Lavasani, H Angepat, D Chiou
IEEE Computer Architecture Letters 13 (2), 57-60, 2013
822013
A reconfigurable fabric for accelerating large-scale datacenter services
A Putnam, AM Caulfield, ES Chung, D Chiou, K Constantinides, J Demme, ...
IEEE Micro 35 (3), 10-22, 2015
772015
Adaptive source routing and packet processing
D Chiou, L Dennison, W Dally
US Patent App. 10/815,458, 2005
692005
StarT-Voyager: A flexible platform for exploring scalable SMP issues
BS Ang, D Chiou, DL Rosenband, M Ehrlich, L Rudolph
SC'98: Proceedings of the 1998 ACM/IEEE Conference on Supercomputing, 26-26, 1998
62*1998
Extending the reach of microprocessors: column and curious caching
D Chiou
Massachusetts Institute of Technology, 1999
561999
The FAST methodology for high-speed SoC/computer simulation
D Chiou, D Sunwoo, J Kim, N Patil, WH Reinhart, DE Johnson, Z Xu
2007 IEEE/ACM International Conference on Computer-Aided Design, 295-302, 2007
50*2007
RAMP: Research accelerator for multiple processors-a community vision for a shared experimental parallel HW/SW platform
Arvind, K Asanovic, D Chiou, JC Hoe, C Kozyrakis, S Lu, M Oskin, ...
UC Berkeley technical report, UCB/CSD-05-1412, 2005
442005
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Articles 1–20