| An asynchronous power aware and adaptive NoC based circuit E Beigné, F Clermidy, H Lhermet, S Miermont, Y Thonnart, XT Tran, ... IEEE Journal of solid-state Circuits 44 (4), 1167-1177, 2009 | 165 | 2009 |
| A fully-asynchronous low-power framework for GALS NoC integration Y Thonnart, P Vivet, F Clermidy 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 141 | 2010 |
| A 477mW NoC-based digital baseband for MIMO 4G SDR F Clermidy, C Bernard, R Lemaire, J Martin, I Miro-Panades, Y Thonnart, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 278-279, 2010 | 124 | 2010 |
| IntAct: A 96-core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, C Fuguet, I Miro-Panades, ... IEEE Journal of Solid-State Circuits 56 (1), 79-97, 2020 | 96 | 2020 |
| 19.2 A 110mK 295µW 28nm FDSOI CMOS quantum integrated circuit with a 2.8 GHz excitation and nA current sensing of an on-chip double quantum dot L Le Guevel, G Billiot, X Jehl, S De Franceschi, M Zurita, Y Thonnart, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 306-308, 2020 | 85 | 2020 |
| 2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm … P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, G Moritz, I Miro-Panadès, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 46-48, 2020 | 69 | 2020 |
| Design and implementation of a GALS adapter for ANoC based architectures Y Thonnart, E Beigné, P Vivet 2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 13-22, 2009 | 66 | 2009 |
| An open and reconfigurable platform for 4g telecommunication: Concepts and application F Clermidy, R Lemaire, X Popon, D Ktenas, Y Thonnart 2009 12th Euromicro conference on digital system design, architectures …, 2009 | 63 | 2009 |
| A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking E Beigne, A Valentian, I Miro-Panades, R Wilson, P Flatresse, F Abouzeid, ... IEEE Journal of Solid-State Circuits 50 (1), 125-136, 2014 | 62 | 2014 |
| A Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links P Vivet, Y Thonnart, R Lemaire, C Santos, E Beigné, C Bernard, F Darve, ... IEEE Journal of Solid-State Circuits 52 (1), 33-49, 2016 | 59 | 2016 |
| A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC D Dutoit, C Bernard, S Chéramy, F Clermidy, Y Thonnart, P Vivet, ... 2013 Symposium on VLSI Technology, C22-C23, 2013 | 58 | 2013 |
| A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 53 | 2014 |
| Efficiency optimization of silicon photonic links in 65-nm CMOS and 28-nm FDSOI technology nodes R Polster, Y Thonnart, G Waltener, JL Gonzalez, E Cassan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (12 …, 2016 | 51 | 2016 |
| A pseudo-synchronous implementation flow for WCHB QDI asynchronous circuits Y Thonnart, E Beigné, P Vivet 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems …, 2012 | 51 | 2012 |
| Silicon photonics for terabit/s communication in data centers and exascale computers S Bernabe, Q Wilmart, K Hasharoni, K Hassan, Y Thonnart, P Tissier, ... Solid-State Electronics 179, 107928, 2021 | 45 | 2021 |
| A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical … Y Thonnart, M Zid, JL Gonzalez-Jimenez, G Waltener, R Polster, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 350-352, 2018 | 45 | 2018 |
| Formal verification of CHP specifications with CADP illustration on an asynchronous network-on-chip G Salaun, W Serwe, Y Thonnart, P Vivet 13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007 | 43 | 2007 |
| An analytical method for evaluating network-on-chip performance S Foroutan, Y Thonnart, R Hersemeule, A Jerraya 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 42 | 2010 |
| POPSTAR: A robust modular optical NoC architecture for chiplet-based 3D integrated systems Y Thonnart, S Bernabé, J Charbonnier, C Bernard, D Coriat, C Fuguet, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 40 | 2020 |
| Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs E Beigné, A Valentian, B Giraud, O Thomas, T Benoist, Y Thonnart, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 613-618, 2013 | 39 | 2013 |
