| Simba: Scaling deep-learning inference with multi-chip-module-based architecture YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 224 | 2019 |
| An agile approach to building RISC-V microprocessors Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ... ieee Micro 36 (2), 8-20, 2016 | 127 | 2016 |
| SRAM assist techniques for operation in a wide voltage range in 28-nm CMOS B Zimmer, SO Toh, H Vo, Y Lee, O Thomas, K Asanovic, B Nikolic IEEE Transactions on Circuits and Systems II: Express Briefs 59 (12), 853-857, 2012 | 91 | 2012 |
| Magnet: A modular accelerator generator for neural networks R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 81 | 2019 |
| A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtić, B Keller, S Bailey, ... IEEE Journal of Solid-State Circuits 51 (4), 930-942, 2016 | 66 | 2016 |
| System and method for performing SRAM write assist BM Zimmer, ME Sinangil US Patent 8,861,290, 2014 | 63 | 2014 |
| A 0.32–128 TOPS, scalable multi-chip-module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... IEEE Journal of Solid-State Circuits 55 (4), 920-932, 2020 | 55 | 2020 |
| A modular digital VLSI flow for high-productivity SoC design B Khailany, R Venkatesan, J Clemons, JS Emer, M Fojtik, A Klinefelter, ... Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 54 | 2018 |
| Analog/mixed-signal hardware error modeling for deep learning inference AS Rekhi, B Zimmer, N Nedovic, N Liu, R Venkatesan, M Wang, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 50 | 2019 |
| A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtic, B Keller, S Bailey, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C316-C317, 2015 | 47 | 2015 |
| A 0.11 pj/op, 0.32-128 tops, scalable multi-chip-module-based deep neural network accelerator with ground-reference signaling in 16nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... 2019 Symposium on VLSI Circuits, C300-C301, 2019 | 46 | 2019 |
| A 1.17-pJ/b, 25-Gb/s/pin ground-referenced single-ended serial link for off-and on-package communication using a process-and temperature-adaptive voltage regulator JW Poulton, JM Wilson, WJ Turner, B Zimmer, X Chen, SS Kudva, S Song, ... IEEE Journal of Solid-State Circuits 54 (1), 43-54, 2018 | 45 | 2018 |
| Strober: Fast and accurate sample-based energy simulation for arbitrary RTL D Kim, A Izraelevitz, C Celio, H Kim, B Zimmer, Y Lee, J Bachrach, ... ACM SIGARCH Computer Architecture News 44 (3), 128-139, 2016 | 43 | 2016 |
| A 28 nm 2 Mbit 6 T SRAM with highly configurable low-voltage write-ability assist implementation and capacitor-based sense-amplifier input offset compensation ME Sinangil, JW Poulton, MR Fojtik, TH Greer, SG Tell, AJ Gotterba, ... IEEE Journal of Solid-State Circuits 51 (2), 557-567, 2015 | 39 | 2015 |
| A 1.17 pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off-and on-package communication in 16nm CMOS using a process-and temperature-adaptive voltage regulator JM Wilson, WJ Turner, JW Poulton, B Zimmer, X Chen, SS Kudva, S Song, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 276-278, 2018 | 37 | 2018 |
| A RISC-V processor SoC with integrated power management at submicrosecond timescales in 28 nm FD-SOI B Keller, M Cochet, B Zimmer, J Kwak, A Puggelli, Y Lee, M Blagojević, ... IEEE Journal of Solid-State Circuits 52 (7), 1863-1875, 2017 | 37 | 2017 |
| Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects WJ Turner, JW Poulton, JM Wilson, X Chen, SG Tell, M Fojtik, TH Greer, ... 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018 | 28 | 2018 |
| 6T SRAM design for wide voltage range in 28nm FDSOI O Thomas, B Zimmer, B Pelloux-Prayer, N Planes, KC Akyel, L Ciampolini, ... 2012 IEEE International SOI Conference (SOI), 1-2, 2012 | 26 | 2012 |
| Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC B Keller, M Cochet, B Zimmer, Y Lee, M Blagojevic, J Kwak, A Puggelli, ... ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 269-272, 2016 | 21 | 2016 |
| Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking Y Lee, B Zimmer, A Waterman, A Puggelli, J Kwak, R Jevtic, B Keller, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-45, 2015 | 21 | 2015 |
Krste AsanovicUC BerkeleyVerified email at berkeley.edu
