| Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width M Ryu, F Bien, Y Kim AIP Advances 6 (1), 2016 | 9 | 2016 |
| Simple and accurate capacitance modeling of 32nm multi-fin FinFET D Kim, Y Kang, M Ryu, Y Kim 2013 International SoC Design Conference (ISOCC), 392-393, 2013 | 8 | 2013 |
| Performance and power analysis of through silicon via based 3D IC integration Y Kim, M Ryu, HV Nguyen International Workshop on System Level Interconnect Prediction, 1-1, 2011 | 7 | 2011 |
| On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor J Lee, M Ryu, Y Kim IEICE Electronics Express 12 (12), 20150321-20150321, 2015 | 6 | 2015 |
| Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits M Ryu, Y Kim JSTS: Journal of Semiconductor Technology and Science 15 (4), 462-470, 2015 | 3 | 2015 |
| Transistor layout optimization for leakage saving M Ryu, Y Kang, Y Kim 2013 International SoC Design Conference (ISOCC), 253-254, 2013 | 3 | 2013 |
| Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shape M Ryu, Y Kim IEICE Electronics Express 10 (11), 20130239-20130239, 2013 | 3 | 2013 |
| A novel methodology for speeding up IC performance in 32nm FinFET HV Nguyen, M Ryu, Y Kim IEICE Electronics Express 9 (4), 227-233, 2012 | 3 | 2012 |
| Diffusion-rounded CMOS for improving both Ion and Ioff characteristics M Ryu, HV Nguyen, Y Kim IEICE Electronics Express 8 (21), 1783-1788, 2011 | 3 | 2011 |
| TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC HV Nguyen, M Ryu, Y Kim IEICE transactions on electronics 95 (12), 1864-1871, 2012 | 1 | 2012 |
| Junctionless Sandwiched-gate Logic Design using Novel Device Structure M Ryu, Y Kim JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 18 (4), 461-467, 2018 | | 2018 |
| Process-induced Structural Variability-aware Performance Optimization for Advanced Nanoscale Technologies M Ryu Graduate School of UNIST, 2016 | | 2016 |
| Sandwiched-gate inverter: Novel device structure for future logic gates M Ryu, F Bien, Y Kim 2015 International Conference on Simulation of Semiconductor Processes and …, 2015 | | 2015 |
| Analysis of structural variation and threshold voltage modulation in 10-nm double gate-all-around (DGAA) transistor M Ryu, Y Kim 2014 International SoC Design Conference (ISOCC), 228-229, 2014 | | 2014 |
| A high resolution and high linearity 45nm CMOS fully digital voltage sensor for low power applications M Ryu, Y Kim IEICE Electronics Express 10 (13), 20130400-20130400, 2013 | | 2013 |
Youngmin KimSchool of Electronic and Electrical Engineering, Hongik University, Seoul, KoreaVerified email at hongik.ac.kr
