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Sriyash Caculo
Sriyash Caculo
Advanced Micro Devices
Verified email at amd.com
Title
Cited by
Cited by
Year
Characterizing the scale-up performance of microservices using teastore
S Caculo, K Lahiri, S Kalambur
2020 IEEE International Symposium on Workload Characterization (IISWC), 48-59, 2020
102020
Efficient architecture for implementation of Hermite interpolation on FPGA
GC George, A Moitra, S Caculo, AA Prince
2018 conference on Design and Architectures for Signal and Image Processing …, 2018
52018
A novel and efficient hardware accelerator architecture for signal normalization
GC George, A Moitra, S Caculo, AA Prince, JJU Buch, SK Pathak
Circuits, Systems, and Signal Processing 39 (5), 2425-2441, 2020
42020
Session: Architectures for efficient numerical computation
F Kästner, M Hübner, GC George, S Caculo, A Moitra, A Prince, A Sapio, ...
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Articles 1–4