Hariklia Deligianni
Hariklia Deligianni
IBM, Thomas J. Watson Research Center
Verified email at us.ibm.com
Cited by
Cited by
Damascene copper electroplating for chip interconnections
PC Andricacos, C Uzoh, JO Dukovic, J Horkans, H Deligianni
IBM Journal of Research and Development 42 (5), 567-574, 1998
A High Efficiency Electrodeposited Cu2ZnSnS4 Solar Cell
S Ahmed, KB Reuter, O Gunawan, L Guo, LT Romankiw, H Deligianni
Advanced Energy Materials 2 (2), 253-259, 2012
The chemistry of additives in damascene copper plating
PM Vereecken, RA Binstead, H Deligianni, PC Andricacos
IBM Journal of Research and Development 49 (1), 3-18, 2005
Planar copperpolyimide back end of the line interconnections for ULSI devices
B Luther
VMIC Conference, 15-21, 1993
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)
AW Topol, DC La Tulipe, L Shi, SM Alam, DJ Frank, SE Steen, J Vichiconti, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
Electrodeposited Cu2ZnSnSe4 thin film solar cell with 7% power conversion efficiency
L Guo, Y Zhu, O Gunawan, T Gokmen, VR Deline, S Ahmed, ...
Progress in Photovoltaics: Research and Applications 22 (1), 58-68, 2014
Flip-Chip interconnections using lead-free solders
PC Andricacos, M Datta, H Deligianni, WJ Horkans, SK Kang, ...
US Patent 6,224,690, 2001
Vertical nanowire FET devices
H Deligianni, Q Huang, LT Romankiw
US Patent 8,637,849, 2014
Role of oxygen vacancies in V/sub FB//V/sub t/stability of pFET metals on HfO/sub 2
E Cartier, FR McFeely, V Narayanan, P Jamison, BP Linder, M Copel, ...
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 230-231, 2005
Selective capping of copper wiring
PC Andricacos, ST Chen, JM Cotte, H Deligianni, M Krishnan, WT Tseng, ...
US Patent 7,008,871, 2006
In situ surface pH measurement during electrolysis using a rotating pH electrode
H Deligianni, LT Romankiw
IBM Journal of Research and Development 37 (2), 85-95, 1993
Methods of manufacture of vertical nanowire FET devices
H Deligianni, Q Huang, LT Romankiw
US Patent 7,892,956, 2011
Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density
VS Basker, JM Cotte, H Deligianni, JU Knickerbocker, KT Kwietniak
US Patent 7,863,189, 2011
Method and system for scheduling the maintenance of remotely monitored devices
B Godwin
US Patent App. 10/304,603, 2003
Effect of fluid flow on convective transport in small cavities
RC Alkire, H Deligianni, JB Ju
Journal of the Electrochemical Society 137 (3), 818, 1990
Copper alloys for chip and package interconnections
PC Andricacos, H Deligianni, JME Harper, CK Hu, DJ Pearson, ...
US Patent 6,063,506, 2000
Emoticon input method for mobile terminal
ST Hyon
US Patent 7,835,729, 2010
The role of mass transport on anisotropic electrochemical pattern etching
R Alkire, H Deligianni
Journal of the Electrochemical Society 135 (5), 1093, 1988
Electrochemical fabrication of mechanically robust PbSn C4 interconnections
M Datta, RV Shenoy, C Jahnes, PC Andricacos, J Horkans, JO Dukovic, ...
Journal of the Electrochemical Society 142 (11), 3779, 1995
Deep filled vias
P Andricacos, EI Cooper, TJ Dalton, H Deligianni, D Guidotti, ...
US Patent 7,060,624, 2006
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