| Didi: Mitigating the performance impact of tlb shootdowns using a shared tlb directory C Villavieja, V Karakostas, L Vilanova, Y Etsion, A Ramirez, A Mendelson, ... 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 154 | 2011 |
| The low-power architecture approach towards exascale computing N Rajovic, N Puzovic, L Vilanova, C Villavieja, A Ramirez Proceedings of the second workshop on Scalable algorithms for large-scale …, 2011 | 116 | 2011 |
| Sinuca: A validated micro-architecture simulator MAZ Alves, C Villavieja, M Diener, FB Moreira, POA Navaux 2015 IEEE 17th International Conference on High Performance Computing and …, 2015 | 63 | 2015 |
| On the simulation of large-scale architectures using multiple application abstraction levels A Rico Carro, F Cabarcas, C Villavieja Prados, M Pavlovic, A Vega, ... ACM transactions on architecture and code optimization 8 (4), 36: 1-36: 20, 2012 | 49 | 2012 |
| Towards an adaptable systems architecture for memory tiering at warehouse-scale P Duraisamy, W Xu, S Hare, R Rajwar, D Culler, Z Xu, J Fan, C Kennelly, ... Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 37 | 2023 |
| On the simulation of large-scale architectures using multiple application abstraction levels A Rico, F Cabarcas, C Villavieja, M Pavlovic, A Vega, Y Etsion, A Ramirez, ... ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-20, 2012 | 30 | 2012 |
| Scalable simulation of decoupled accelerator architectures A Rico, F Cabarcas, A Quesada, M Pavlovic, AJ Vega, C Villavieja, ... Universitat Politecnica de Catalunya, Tech. Rep. UPCDAC-RR-2010-14, 2010 | 26 | 2010 |
| Energy savings via dead sub-block prediction MAZ Alves, E Ebrahimi, VT Narasiman, C Villavieja, POA Navaux, YN Patt 2012 IEEE 24th International Symposium on Computer Architecture and High …, 2012 | 23 | 2012 |
| Yoga: A hybrid dynamic VLIW/OoO processor C Villavieja, JA Joao, R Miftakhutdinov, YN Patt no. HPS Technical Report, 2014 | 16 | 2014 |
| Adaptive runtime-assisted block prefetching on chip-multiprocessors V Garcia, A Rico, C Villavieja, P Carpenter, N Navarro, A Ramirez International journal of parallel programming 45, 530-550, 2017 | 10 | 2017 |
| FELI: HW/SW support for on-chip distributed shared memory in multicores C Villavieja, Y Etsion, A Ramirez, N Navarro Euro-Par 2011 Parallel Processing: 17th International Conference, Euro-Par …, 2011 | 10 | 2011 |
| Memory management on chip-multiprocessors with on-chip memories C Villavieja, I Gelado, A Ramirez, N Navarro Proc. Workshop on the Interaction between Operating Systems and Computer …, 2008 | 7 | 2008 |
| Scalable simulation of decoupled accelerator architectures. Universitat Politecnica de Catalunya A Rico, F Cabarcas, A Quesada, M Pavlovic, AJ Vega, C Villavieja, ... Tech. Rep. UPCDACRR-2010-14, 2010 | 6 | 2010 |
| Energy efficient last level caches via last read/write prediction MAZ Alves, C Villavieja, M Diener, POA Navaux 2013 25th International Symposium on Computer Architecture and High …, 2013 | 5 | 2013 |
| Physics-based time-domain model of a magnetic induction microgenerator L Mateu, C Villavieja, F Moll IEEE transactions on magnetics 43 (3), 992-1001, 2007 | 5 | 2007 |
| Aplicación de herramientas tecnológicas en la evaluación del proceso de enseñanza-aprendizaje: Uso de Smartphones en el aula A Peña Cerdán, A Palomares Chust, D Andrés Martínez, ... TEXTOS. Revista Internacional de Aprendizaje y Cibersociedad 17 (1), 11-34, 2013 | 4 | 2013 |
| Cómo evaluar continua e individualmente en asignaturas basadas en proyectos L Velasco, C Villavieja Asociación de Enseñantes Universitarios de la Informática (AENUI), 2009 | 4 | 2009 |
| On the simulation of large-scale architectures using multiple application abstraction levels. 2015 A Rico, F Cabarcas, C Villavieja, M Pavlovic, A Vega, Y Etsion, A Ramirez, ... ACM Trans. Archit. Code Optim 8 (4), 0 | 3 | |
| The Data Transfer Engine: Towards a Software Controlled Memory Hierarchy V Garcia, A Rico, C Villavieja, N Navarro, A Ramirez Advanced Computer Architecture and Compilation for Embedded Systems, 215-218, 2012 | 2 | 2012 |
| Hardware Support for Explicit Communication in Scalable CMP’s C Villavieja, M Katevenis, N Navarro, D Pnevmatikatos, A Ramirez, ... Computer Architecture Dept., Polythecnic University of Catalonia (UPC …, 2008 | 2 | 2008 |
Alex RamirezGoogleVerified email at google.com
