| Larrabee: a many-core x86 architecture for visual computing L Seiler, D Carmean, E Sprangle, T Forsyth, M Abrash, P Dubey, ... ACM Transactions on Graphics (TOG) 27 (3), 1-15, 2008 | 1216 | 2008 |
| Asim: A performance model framework J Emer, P Ahuja, E Borch, A Klauser, CK Luk, S Manne, SS Mukherjee, ... Computer 35 (2), 68-76, 2002 | 322 | 2002 |
| Dynamic history-length fitting: A third level of adaptivity for branch prediction T Juan, S Sanjeevan, JJ Navarro Proceedings of the 25th Annual International Symposium on Computer …, 1998 | 188 | 1998 |
| Reducing TLB power requirements T Juan, T Lang, JJ Navarro Proceedings of the 1997 international symposium on Low power electronics and …, 1997 | 154 | 1997 |
| Larrabee: A many-core x86 architecture for visual computing L Seiler, D Carmean, E Sprangle, T Forsyth, P Dubey, S Junkins, A Lake, ... IEEE micro 29 (1), 10-21, 2009 | 151 | 2009 |
| Tarantula: a vector extension to the alpha architecture R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ... ACM SIGARCH Computer Architecture News 30 (2), 281-292, 2002 | 151 | 2002 |
| Dataflow analysis of branch mispredictions and its application to early resolution of branch outcomes A Farcy, O Temam, R Espasa, T Juan Proceedings. 31st Annual ACM/IEEE International Symposium on …, 1998 | 108 | 1998 |
| Implementing vector memory operations R Espasa, J Emer, G Lowney, R Gramunt, S Galan, T Juan, J Corbal, ... US Patent 7,627,735, 2009 | 65 | 2009 |
| Data caches for superscalar processors T Juan, JJ Navarro, O Temam Proceedings of the 11th international conference on Supercomputing, 60-67, 1997 | 65 | 1997 |
| The difference-bit cache T Juan, T Lang, JJ Navarro Proceedings of the 23rd annual international symposium on Computer …, 1996 | 61 | 1996 |
| MOB forms: A class of Multilevel Block Algorithms for dense linear algebra operations JJ Navarro, T Juan, T Lang Proceedings of the 8th international conference on Supercomputing, 354-363, 1994 | 57 | 1994 |
| How to compare the performance of two SMT microarchitectures. Y Sazeides, T Juan ISPASS, 180-183, 2001 | 33 | 2001 |
| Block algorithms for sparse matrix computations on high performance workstations JJ Navarro, E García-Diego, JL Larriba-Pey, T Juan Proceedings of the 10th international conference on Supercomputing, 301-308, 1996 | 29 | 1996 |
| Adaptively handling remote atomic execution based upon contention prediction JB Fryman, ET Grochowski, T Juan, AT Forsyth, J Mejia, R Sundararaman, ... US Patent 8,533,436, 2013 | 25 | 2013 |
| Store sets poison propagation T Juan, G Chrysos, C Gianos, E Borch US Patent App. 10/034,219, 2003 | 21 | 2003 |
| Dynamic cache splitting T Juan, D Royo, JJ Navarro XV International Confernce of the Chilean Computational Society, 1995 | 19 | 1995 |
| Architecting a hardware-managed hybrid DIMM optimized for cost/performance F Ware, J Bueno, L Gopalakrishnan, B Haukness, C Haywood, T Juan, ... Proceedings of the International Symposium on Memory Systems, 327-340, 2018 | 6 | 2018 |
| Implementing vector memory operations R Espasa, J Emer, G Lowney, R Gramunt, S Galan, T Juan, J Corbal, ... US Patent 8,707,012, 2014 | 5 | 2014 |
| Reusing cached schedules in an out-of-order processor with in-order issue logic O Palomar, T Juan, JJ Navarro 2009 IEEE International Conference on Computer Design, 246-253, 2009 | 4 | 2009 |
| Block algorithms to speed up the sparse matrix by dense matrix multiplication on high performance workstations E Garcia, JL Larriba-Pey, T Juan, T Lang, JJ Navarro MA Rep., UPCDAC-1995-3, University Polytechnics of Catalunya, Barcelona, Spain, 1995 | 3 | 1995 |
