Bipin Rajendran
Bipin Rajendran
Professor of Intelligent Computing Systems at King's College London
Verified email at - Homepage
Cited by
Cited by
Phase change memory
HSP Wong, S Raoux, SB Kim, J Liang, JP Reifenberg, B Rajendran, ...
Proceedings of the IEEE 98 (12), 2201-2227, 2010
Phase change memory technology
GW Burr, MJ Breitwisch, M Franceschini, D Garetto, K Gopalakrishnan, ...
Journal of Vacuum Science & Technology B 28 (2), 223-262, 2010
Neuromorphic computing with multi-memristive synapses
I Boybat, M Le Gallo, SR Nandakumar, T Moraitis, T Parnell, T Tuma, ...
Nature communications 9 (1), 2514, 2018
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
J Seo, B Brezzo, Y Liu, BD Parker, SK Esser, RK Montoye, B Rajendran, ...
2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011
Accurate deep neural network inference using computational phase-change memory
V Joshi, M Le Gallo, S Haefeli, I Boybat, SR Nandakumar, C Piveteau, ...
Nature communications 11 (1), 2473, 2020
Write strategies for 2 and 4-bit multi-level phase-change memory
T Nirschl, JB Philipp, TD Happ, GW Burr, B Rajendran, MH Lee, A Schrott, ...
2007 IEEE International Electron Devices Meeting, 461-464, 2007
Sequential 3D IC fabrication: Challenges and prospects
B Rajendran
Proceedings of VLSI Multi Level Interconnect Conference, 57-64, 2006
Nano-graphoepitaxy of semiconductors for 3D integration
F Crnogorac, DJ Witte, Q Xia, B Rajendran, DS Pickard, Z Liu, A Mehta, ...
Microelectronic Engineering 84 (5-8), 891-894, 2007
Thermal Simulation of Laser Annealing for 3D Integration
B Rajendran, SH Jain, TA Kramer, RFW Pease
VMIC, 2003
Electrical Integrity of MOS Devices in Laser Annealed 3D IC Structures
B Rajendran, RS Shenoy, MO Thompson, RFW Pease
proceedings VLSI Multi Level Interconnect Conference, 73-74, 2004
CMOS transistor processing compatible with monolithic 3-D Integration
B Rajendran, RS Shenoy, DJ Witte, NS Chokshi, RL DeLeon, GS Tompa, ...
International VLSI Multilevel Interconnection Conference, 2005
Memristors—From in‐memory computing, deep learning acceleration, and spiking neural networks to the future of neuromorphic and bio‐inspired computing
A Mehonic, A Sebastian, B Rajendran, O Simeone, E Vasilaki, AJ Kenyon
Advanced Intelligent Systems 2 (11), 2000085, 2020
Nanoscale electronic synapses using phase change devices
BL Jackson, B Rajendran, GS Corrado, M Breitwisch, GW Burr, R Cheek, ...
ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (2), 1-20, 2013
Specifications of nanoscale devices and circuits for neuromorphic computational systems
B Rajendran, Y Liu, J Seo, K Gopalakrishnan, L Chang, DJ Friedman, ...
IEEE Transactions on Electron Devices 60 (1), 246-253, 2012
Spiking neural networks for handwritten digit recognition—Supervised learning and network optimization
SR Kulkarni, B Rajendran
Neural Networks 103, 118-127, 2018
Phase Change Memory: From Devices to Systems
MK Qureshi, S Gurumurthi, B Rajendran
Synthesis Lectures on Computer Architecture 6 (4), 1-134, 2011
Silicon nanowires for sequence-specific DNA sensing: device fabrication and simulation
Z Li, B Rajendran, TI Kamins, X Li, Y Chen, RS Williams
Applied Physics A 80, 1257-1263, 2005
Low-Power Neuromorphic Hardware for Signal Processing Applications: A review of architectural and system-level design approaches
B Rajendran, A Sebastian, M Schmuker, N Srinivasa, E Eleftheriou
IEEE Signal Processing Magazine, 2019
Efficient Scrub Mechanisms for Error-Prone Emerging Memories
M Awasthi, M Shevgoor, K Sudan, B Rajendran, R Balasubramonian, ...
IEEE International Symposium on High Performance Computer Architecture, 2012
Novel lithography-independent pore phase change memory
M Breitwisch, T Nirschl, CF Chen, Y Zhu, MH Lee, M Lamorey, GW Burr, ...
2007 IEEE Symposium on VLSI Technology, 100-101, 2007
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