| A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking A Santiccioli, M Mercandelli, L Bertulessi, A Parisi, D Cherniak, AL Lacaita, ... IEEE Journal of Solid-State Circuits 55 (12), 3349 - 3361, 2020 | 76 | 2020 |
| 17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking A Santiccioli, M Mercandelli, L Bertulessi, A Parisi, D Cherniak, AL Lacaita, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 268-270, 2020 | 76 | 2020 |
| A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter M Mercandelli, A Santiccioli, A Parisi, L Bertulessi, D Cherniak, AL Lacaita, ... IEEE Journal of Solid-State Circuits 57 (2), 505-517, 2021 | 68 | 2021 |
| A 1.6-to-3.0-GHz Fractional- MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power A Santiccioli, M Mercandelli, AL Lacaita, C Samori, S Levantino IEEE Journal of Solid-State Circuits 54 (11), 3149-3160, 2019 | 37 | 2019 |
| A 1.6-to-3.0-GHz Fractional- MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power A Santiccioli, M Mercandelli, AL Lacaita, C Samori, S Levantino IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 1-4, 2019 | 37 | 2019 |
| A comprehensive phase noise analysis of bang-bang digital PLLs L Avallone, M Mercandelli, A Santiccioli, MP Kennedy, S Levantino, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (7), 2775-2786, 2021 | 24 | 2021 |
| Power‐jitter trade‐off analysis in digital‐to‐time converters A Santiccioli, C Samori, AL Lacaita, S Levantino Electronics Letters 53 (5), 306-308, 2017 | 19 | 2017 |
| A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 17 | 2022 |
| Time-variant modeling and analysis of multiplying delay-locked loops A Santiccioli, C Samori, AL Lacaita, S Levantino IEEE Transactions on Circuits and Systems I: Regular Papers 66 (10), 3775-3785, 2019 | 15 | 2019 |
| 32.3 A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter M Mercandelli, A Santiccioli, SM Dartizio, A Shehata, F Tesolin, S Karman, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 445-447, 2021 | 14 | 2021 |
| A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping SM Dartizio, F Tesolin, M Mercandelli, A Santiccioli, A Shehata, S Karman, ... IEEE Journal of Solid-State Circuits 57 (6), 1723-1735, 2021 | 11 | 2021 |
| 32.8 A 98.4 fs-jitter 12.9-to-15.1 GHz PLL-based LO phase-shifting system with digital background phase-offset correction for integrated phased arrays A Santiccioli, M Mercandelli, SM Dartizio, F Tesolin, S Karman, A Shehata, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 456-458, 2021 | 10 | 2021 |
| A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking … SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... IEEE Journal of Solid-State Circuits 57 (12), 3538-3551, 2022 | 8 | 2022 |
| A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | 5 | 2022 |
| A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... IEEE Journal of Solid-State Circuits 58 (3), 634-646, 2022 | 3 | 2022 |
| Phase locked loop with parallel phase detection circuits D Cherniak, S Levantino, A Santiccioli US Patent 11,418,199, 2022 | 3 | 2022 |
| A 250-Mb/s direct phase modulator with− 42.4-dB EVM based on a 14-GHz digital PLL D Cherniak, M Mercandelli, L Bertulessi, F Padovan, L Grimaldi, ... IEEE Solid-State Circuits Letters 3, 126-129, 2020 | 2 | 2020 |
| A novel LO phase-shifting system based on digital bang-bang PLLs with background phase-offset correction for integrated phased arrays F Tesolin, SM Dartizio, F Buccoleri, A Santiccioli, L Bertulessi, C Samori, ... IEEE Journal of Solid-State Circuits, 2023 | 1 | 2023 |
| Inductorless Frequency Synthesizers for Low-Cost Wireless A Santiccioli Special Topics in Information Technology, 37-50, 2021 | | 2021 |
| Low-Phase-Noise PLL via Reference Path Coupling D Cherniak, S Levantino, A Santiccioli | | 2021 |
Salvatore LevantinoPolitecnico di MilanoVerified email at polimi.it
