| Processor using mini-cores YH Park, K Prasad, H Yang, YB Lee US Patent App. 14/324,302, 2015 | 51 | 2015 |
| A space-and energy-efficient code compression/decompression technique for coarse-grained reconfigurable architectures B Egger, H Lee, D Kang, MS Moghaddam, Y Cho, Y Lee, S Kim, S Ha, ... 2017 IEEE/ACM International Symposium on Code Generation and Optimization …, 2017 | 16 | 2017 |
| On-chip dynamic signal sequence slicing for efficient post-silicon debugging Y Lee, T Matsumoto, M Fujita 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 719-724, 2011 | 14 | 2011 |
| Method of scheduling loops for processor having a plurality of functional units YB Lee, YH Park, H Yang, K Prasad US Patent 9,292,287, 2016 | 11 | 2016 |
| AIX: A high performance and energy efficient inference accelerator on FPGA for a DNN-based commercial speech recognition M Ahn, SJ Hwang, W Kim, S Jung, Y Lee, M Chung, W Lim, Y Kim 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 4 | 2019 |
| Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging Y Lee, T Matsumoto, M Fujita 2010 IEEE International Conference on Computer Design, 402-408, 2010 | 4 | 2010 |
| A post-silicon debug support using high-level design description Y Lee, T Nishihara, T Matsumoto, M Fujita 2009 Asian Test Symposium, 137-142, 2009 | 3 | 2009 |
| Software-based giga-bit WLAN platform H Yang, J Shim, J Bang, Y Lee 2014 IEEE International Conference on Consumer Electronics (ICCE), 478-479, 2014 | 2 | 2014 |
| Online speech dereverberation using RLS-WPE based on a full spatial correlation matrix integrated in a speech enhancement system JH Kim, J Park, M Ahn, Y Lee, W Kim, HM Park 2018 16th International Workshop on Acoustic Signal Enhancement (IWAENC), 36-40, 2018 | 1 | 2018 |
| Scalable radio processor architecture for modern wireless communications YH Park, K Prasad, Y Lee, K Bae, H Yang 2014 International Conference on Field-Programmable Technology (FPT), 310-313, 2014 | 1 | 2014 |
| An automatic method of mapping i/o sequences of chip execution onto high-level design for post-silicon debugging Y Lee, T Matsumoto, M Fujita IEICE transactions on fundamentals of electronics, communications and …, 2011 | 1 | 2011 |
| 既存設計の再利用を考慮した SoC の仕様記述手法と上位設計方法論 李蓮福， 石川悠司， 小島慶久， 吉田浩章， 余宮尚志， 小松聡， 藤田昌宏 電子情報通信学会技術研究報告 107 (505), 49-54, 2008 | 1 | 2008 |
| ハードウェア設計における設計資産の仕様記述およびその検証手法 石川悠司， 李蓮福 電子情報通信学会技術研究報告= IEICE technical report: 信学技報 106 (550), 43-48, 2007 | 1 | 2007 |
| Electronic device, reconfigurable processor and controlling methods thereof B Egger, H Lee, Y Lee, S Kim | | 2018 |
| Communication network setting method of wireless communication terminal JW Shim, JH Bang, YB Lee, H Yang US Patent 9,848,377, 2017 | | 2017 |
| Method and apparatus for shuffling data using hierarchical shuffle units K Prasad, N Basutkar, YH Park, H Yang, YB Lee US Patent 9,841,979, 2017 | | 2017 |
| Electronic apparatus, processor and control method thereof Y Lee, M Kim, S Kim US Patent App. 20,180/088,954, 2017 | | 2017 |
| Ultra-low-power voice trigger for wearable devices DH Kim, S Jo, K Kwon, Y Lee, S Lee, YH Park, S Kim, J Kim, S Lee 2015 IEEE International Conference on Consumer Electronics-Taiwan, 76-77, 2015 | | 2015 |
| Ultra-low-power DSP for Audio Signal Processing K Kwon, M Ahn, S Jo, Y Lee, S Lee, YH Park, S Kim, DH Kim, J Kim Proceedings of the Korean Society of Broadcast Engineers Conference, 157-159, 2014 | | 2014 |
| Utilizing high level design information to speed up post-silicon debugging M Fujita 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 301-305, 2011 | | 2011 |
