Alexander Fell
Alexander Fell
Singapore Institute of Technology
Verified email at iiitd.ac.in - Homepage
Title
Cited by
Cited by
Year
Redefine: Runtime reconfigurable polymorphic asic
M Alle, K Varadarajan, A Fell, N Joseph, S Das, P Biswas, J Chetia, A Rao, ...
ACM Transactions on Embedded Computing Systems (TECS) 9 (2), 1-48, 2009
582009
Compiling techniques for coarse grained runtime reconfigurable architectures
M Alle, K Varadarajan, A Fell, SK Nandy, R Narayan
International Workshop on Applied Reconfigurable Computing, 204-215, 2009
252009
Force-directed scheduling for data flow graph mapping on coarse-grained reconfigurable architectures
A Fell, ZE RŠkossy, A Chattopadhyay
2014 International Conference on ReConFigurable Computing and FPGAs†…, 2014
212014
Synthesis of application accelerators on Runtime Reconfigurable Hardware
M Alle, K Varadarajan, RC Ramesh, J Nimmy, A Fell, A Rao, SK Nandy, ...
2008 International Conference on Application-Specific Systems, Architectures†…, 2008
172008
Generic routing rules and a scalable access enhancement for the network-on-chip reconnect
A Fell, P Biswas, J Chetia, SK Nandy, R Narayan
2009 IEEE International SOC Conference (SOCC), 251-254, 2009
162009
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router
N Joseph, CR Reddy, K Varadarajan, M Alle, A Fell, SK Nandy, ...
ASAP’08: Proceedings of the 19th IEEE International Conference on†…, 2008
142008
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router
J Nimmy, CR Reddy, K Varadarajan, M Alle, A Fell, SK Nandy, R Narayan
2008 International Conference on Application-Specific Systems, Architectures†…, 2008
132008
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration
A Fell, M Alle, K Varadarajan, P Biswas, S Das, J Chetia, SK Nandy, ...
Proceedings of the 2009 international conference on Compilers, architecture†…, 2009
122009
Ramesh Reddy C., Nimmy Joseph, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsh Rao, SK Nandy, and Ranjani Narayan. REDEFINE: Runtime reconfigurable polymorphic ASIC
M Alle, K Varadarajan, A Fell
ACM Transactions on Embedded Computing Systems (TECS) 9 (2), 1-48, 2009
122009
RRC, N
M Alle, K Varadarajan, A Fell
Joseph, S. Das, P. Biswas, J. Chetia, A. Rao, SK Nandy, and R. Narayan†…, 2009
92009
A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI
R Kaur, A Fell, H Rawat
2015 28th IEEE International System-on-Chip Conference (SOCC), 310-315, 2015
52015
RECONNECT: A flexible Router Architecture for Network-on-Chips
A Fell
Indian Institute of Science Bangalore, 2012
52012
Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, SK Nandy, and Ranjani Narayan. Streaming fft on redefine-v2: an application-architecture†…
A Fell
Proceedings of the 2009 international conference on Compilers, architecture†…, 2009
52009
TAD: time side-channel attack defense of obfuscated source code
A Fell, HT Pham, SK Lam
Proceedings of the 24th Asia and South Pacific Design Automation Conference†…, 2019
32019
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems
G Narang, A Fell, PR Gupta, A Grover
2015 28th IEEE International System-on-Chip Conference (SOCC), 105-110, 2015
32015
Cidpro: Custom instructions for dynamic program diversification
TH Pham, A Fell, AK Biswas, SK Lam, N Veeranna
2018 28th International Conference on Field Programmable Logic and†…, 2018
22018
Executable model based design methodology for fast prototyping of mobile network protocol: A case study on MIPI LLI
RK Shah, T Kumar, A Fell, MS Dohadwala, R Malik
2017 4th International Conference on Signal Processing and Integrated†…, 2017
22017
DFGenTool: A dataflow graph generation tool for coarse grain reconfigurable architectures
M Mukherjee, A Fell, A Guha
2017 30th International Conference on VLSI Design and 2017 16th†…, 2017
22017
Method and System on Chip (SoC) for Adapting a Reconfigurable Hardware for an Application at Runtime
SK Nandy, R Narayan, M Alle, K Vardarajan, A Fell, A Rao, R Reddy, ...
US Patent App. 13/002,329, 2011
22011
Automated, inter-macro channel space adjustment and optimization for faster design closure
P Kumar, A Fell, S Mathur
2017 30th IEEE International System-on-Chip Conference (SOCC), 74-79, 2017
12017
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