Follow
Lawrence Pileggi
Lawrence Pileggi
Coraluppi Head and Tanoto Professor of ECE, Carnegie Mellon University
Verified email at andrew.cmu.edu
Title
Cited by
Cited by
Year
Asymptotic waveform evaluation for timing analysis
LT Pillage, RA Rohrer
IEEE transactions on computer-aided design of integrated circuits and …, 1990
23721990
PRIMA: Passive reduced-order interconnect macromodeling algorithm
A Odabasioglu, M Celik, LT Pileggi
The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design, 433-450, 2003
20682003
Electronic Circuit & System Simulation Methods (SRE)
L Pillage
McGraw-Hill, Inc., 1998
5931998
Modeling the" Effective capacitance" for the RC interconnect of CMOS gates
J Qian, S Pullela, L Pillage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994
4411994
IC interconnect analysis
M Celik, L Pileggi, A Odabasioglu
Springer Science & Business Media, 2002
3632002
The Elmore delay as bound for RC trees with generalized input signals
R Gupta, B Krauter, B Tutuianu, J Willis, LT Pileggi
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 364-369, 1995
3341995
Energy-efficient abundant-data computing: The N3XT 1,000 x
MMS Aly, M Gao, G Hills, CS Lee, G Pitner, MM Shulaker, TF Wu, ...
Computer 48 (12), 24-33, 2015
2822015
Digital circuit design challenges and opportunities in the era of nanoscale CMOS
BH Calhoun, Y Cao, X Li, K Mai, LT Pileggi, RA Rutenbar, KL Shepard
Proceedings of the IEEE 96 (2), 343-365, 2008
2682008
Programmable gate array based on configurable metal interconnect vias
L Pileggi, H Schmit
US Patent 6,633,182, 2003
2682003
RICE: Rapid interconnect circuit evaluation using AWE
CL Ratzlaff, LT Pillage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994
2451994
Why do people tag? Motivations for photo tagging
O Nov, C Ye
Communications of the ACM 53 (7), 128-131, 2010
242*2010
Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features
LT Pileggi, AJ Strojwas, LL Lanza
US Patent 7,278,118, 2007
229*2007
Correlation-aware statistical timing analysis with non-Gaussian delay distributions
Y Zhan, AJ Strojwas, X Li, LT Pileggi, D Newmark, M Sharma
Proceedings of the 42nd annual Design Automation Conference, 77-82, 2005
2292005
Performance computation for precharacterized CMOS gates with RC loads
F Dartu, N Menezes, LT Pileggi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996
2061996
RICE: Rapid interconnect circuit evaluator
CL Ratzlaff, N Gopal, LT Pillage
Proceedings of the 28th ACM/IEEE Design Automation Conference, 555-560, 1991
2061991
Calculating worst-case gate delays due to dominant capacitance coupling
F Dartu, LT Pileggi
Proceedings of the 34th annual Design Automation Conference, 46-51, 1997
2041997
Model order-reduction of RC (L) interconnect including variational analysis
Y Liu, LT Pileggi, AJ Strojwas
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 201-206, 1999
1981999
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Y Liu, SR Nassif, LT Pileggi, AJ Strojwas
Proceedings of the 37th Annual Design Automation Conference, 168-171, 2000
1792000
Exact combinatorial optimization methods for physical design of regular logic bricks
B Taylor, L Pileggi
Proceedings of the 44th annual Design Automation Conference, 344-349, 2007
1732007
STAC: Statistical timing analysis with correlation
J Le, X Li, LT Pileggi
Proceedings of the 41st annual Design Automation Conference, 343-348, 2004
1672004
The system can't perform the operation now. Try again later.
Articles 1–20