Zhibo Wang
Zhibo Wang
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Sticker: A 0.41-62.1 TOPS/W 8Bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers
Z Yuan, J Yue, H Yang, Z Wang, J Li, Y Yang, Q Guo, X Li, MF Chang, ...
2018 IEEE symposium on VLSI circuits, 33-34, 2018
A 65nm ReRAM-enabled nonvolatile processor with 6x reduction in restore time and 4x higher clock frequency using adaptive data retention and self-write-termination nonvolatile …
Y Liu, Z Wang, A Lee, F Su, CP Lo, Z Yuan, CC Lin, Q Wei, Y Wang, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 84-86, 2016
A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory
F Su, WH Chen, L Xia, CP Lo, T Tang, Z Wang, KH Hsu, M Cheng, JY Li, ...
2017 Symposium on VLSI Technology, T260-T261, 2017
An energy-efficient heterogeneous dual-core processor for Internet of Things
Z Wang, Y Liu, Y Sun, Y Li, D Zhang, H Yang
2015 IEEE international symposium on circuits and systems (ISCAS), 2301-2304, 2015
A ReRAM-based nonvolatile flip-flop with self-write-termination scheme for frequent-OFF fast-wake-up nonvolatile processors
A Lee, CP Lo, CC Lin, WH Chen, KH Hsu, Z Wang, F Su, Z Yuan, Q Wei, ...
IEEE Journal of Solid-State Circuits 52 (8), 2194-2207, 2017
7.5 A 65nm 0.39-to-140.3 TOPS/W 1-to-12b unified neural network processor using block-circulant-enabled transpose-domain acceleration with 8.1× higher TOPS/mm 2 and 6T HBST …
J Yue, R Liu, W Sun, Z Yuan, Z Wang, YN Tu, YJ Chen, A Ren, Y Wang, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 138-140, 2019
A 3.77 TOPS/W convolutional neural network processor with priority-driven kernel optimization
J Yue, Y Liu, Z Yuan, Z Wang, Q Guo, J Li, C Yang, H Yang
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (2), 277-281, 2018
A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for …
CP Lo, WH Chen, Z Wang, A Lee, KH Hsu, F Su, YC King, CJ Lin, Y Liu, ...
2016 IEEE international electron devices meeting (IEDM), 16.3. 1-16.3. 4, 2016
NEOFog: Nonvolatility-exploiting optimizations for fog computing
K Ma, X Li, MT Kandemir, J Sampson, V Narayanan, J Li, T Wu, Z Wang, ...
Proceedings of the Twenty-Third International Conference on Architectural …, 2018
A 130-nm ferroelectric nonvolatile system-on-chip with direct peripheral restore architecture for transient computing system
Y Liu, F Su, Y Yang, Z Wang, Y Wang, Z Li, X Li, R Yoshimura, T Naiki, ...
IEEE Journal of Solid-State Circuits 54 (3), 885-895, 2019
A 130nm FeRAM-based parallel recovery nonvolatile SOC for normally-OFF operations with 3.9× faster running speed and 11× higher energy efficiency using fast power-on detection …
Z Wang, F Su, Y Wang, Z Li, X Li, R Yoshimura, T Naiki, T Tsuwa, T Saito, ...
2017 Symposium on VLSI Circuits, C336-C337, 2017
A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving $> 4\times $ Faster Clock Frequency and $> 6\times $ Higher …
Z Wang, Y Liu, A Lee, F Su, CP Lo, Z Yuan, J Li, CC Lin, WH Chen, ...
IEEE Journal of Solid-State Circuits 52 (10), 2769-2785, 2017
Design exploration of inrush current aware controller for nonvolatile processor
Y Liu, F Su, Z Wangy, H Yang
Non-Volatile Memory System and Applications Symposium (NVMSA), 2015 IEEE, 1-6, 2015
Design of nonvolatile processors and applications
F Su, Z Wang, J Li, MF Chang, Y Liu
2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016
A 2.2-GHz configurable direct digital frequency synthesizer based on LUT and rotation
Y Yang, X Shi, F Su, Z Wang, P Yang, H Yang, Y Liu
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (5), 1970-1980, 2018
AERIS: Area/Energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip
J Yue, Y Liu, F Su, S Li, Z Yuan, Z Wang, W Sun, X Li, H Yang
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
A 2-GHz direct digital frequency synthesizer based on LUT and rotation
Y Yang, Z Wang, P Yang, MF Chang, MS Ho, H Yang, Y Liu
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
Multistage function speculation adders
Y Sun, Y Liu, Z Wang, H Yang
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2015
A compare-and-select error tolerant scheme for nonvolatile processors
Z Wang, R Hua, Y Liu, H Yang
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016
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