| Method and circuit to enable wide supply voltage difference in multi-supply memory P Jain, V Asthana, N Batra US Patent 9,508,405, 2016 | 32 | 2016 |
| Method, system and device for non-volatile memory device operation AJ Bhavnagarwala, V Asthana, P Agarwal, A Kumar, L Shifren US Patent 9,947,402, 2018 | 23 | 2018 |
| Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control V Asthana, M Kar, J Jimenez, JP Noel, S Haendler, P Galy 2013 Proceedings of the ESSCIRC (ESSCIRC), 415-418, 2013 | 15 | 2013 |
| Read assist circuitry for memory applications A Singh, V Asthana, M Rathore, A Goel, N Kaushik, R Ahuja, R Mathur, ... US Patent 10,854,280, 2020 | 10 | 2020 |
| Write operation scheme for SRAM A Goel, SK Banik, LK Saini, V Asthana US Patent 10,199,094, 2019 | 5 | 2019 |
| SRAM bitcell implemented in double gate technology V Asthana, M Kar, P Galy, J Jimenez US Patent 9,159,402, 2015 | 4 | 2015 |
| 6T SRAM performance and power gain using Double Gate MOS in 28nm FDSOI Technology V Asthana, M Kar, J Jimenez, S Haendler, P Galy Proceedings of 2013 International Conference on IC Design & Technology …, 2013 | 4 | 2013 |
| Dummy wordline underdrive circuitry V Asthana, N Jindal, N Kaushik, K Mittal, D Gupta, S Malik, S Bhavsar US Patent 10,217,506, 2019 | 3 | 2019 |
| Read only memory device with bitline leakage reduction K Chatterjee, V Asthana, J Dasani US Patent App. 11/648,155, 2007 | 3 | 2007 |
| Configurable integrated circuits YK Chong, S Thyagarajan, AW Chen, V Asthana, M Kumar US Patent 10,978,141, 2021 | 2 | 2021 |
| 0.25 pA/Bit ultra-low-leakage 6T single-port SRAM on 22nm bulk process for IoT applications V Asthana, MJ Kumar, A Kulshrestha, M Kumar, SK Banik, S Aggarwal 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 2 | 2020 |
| Method and circuit to enable wide supply voltage difference in multi-supply memory P Jain, V Asthana, N Batra US Patent 10,468,095, 2019 | 1 | 2019 |
| Method and circuit to enable wide supply voltage difference in multi-supply memory P Jain, V Asthana, N Batra US Patent 10,008,258, 2018 | 1 | 2018 |
| Analytical modeling of sub-onset current of tunnel field effect transistor P Singh, V Asthana, R Sithanandam, A Bulusu, SD Gupta 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 1 | 2014 |
| Read assist circuitry for memory applications R Mathur, V Asthana, AG Goel, N Kaushik, R Ahuja, B Maiti, YK Chong US Patent 11,475,944, 2022 | | 2022 |
| 5GHz SRAM for High-Performance Compute Platform in 5nm CMOS R Mathur, M Kumar, V Asthana, S Aggarwal, S Gupta, D Wanjul, ... 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | | 2022 |
| Fault detection circuitry V Asthana, J Dasani, A Chhabra US Patent 10,848,186, 2020 | | 2020 |
| Method, system and device for non-volatile memory device operation AJ Bhavnagarwala, V Asthana, P Agarwal, A Kumar, L Shifren US Patent 10,431,304, 2019 | | 2019 |
| Power-on-reset circuit L Gupta, V Nautiyal, AW Chen, J Dasani, B Zheng, A Kumar, V Asthana US Patent 10,425,076, 2019 | | 2019 |
| Bypass circuitry for memory applications V Asthana, N Jindal, SK Banik US Patent 10,418,124, 2019 | | 2019 |
