| K longest paths per gate (KLPG) test generation for scan-based sequential circuits W Qiu, J Wang, DMH Walker, D Reddy, X Lu, Z Li, W Shi, H Balachandran 2004 International Conferce on Test, 223-231, 2004 | 149 | 2004 |
| A fast algorithm for optimal buffer insertion W Shi, Z Li Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2005 | 122* | 2005 |
| The ISPD-2011 routability-driven placement contest and benchmark suite N Viswanathan, CJ Alpert, C Sze, Z Li, GJ Nam, JA Roy Proceedings of the 2011 international symposium on Physical design, 141-146, 2011 | 115 | 2011 |
| The DAC 2012 routability-driven placement contest and benchmark suite N Viswanathan, C Alpert, C Sze, Z Li, Y Wei Proceedings of the 49th Annual Design Automation Conference, 774-782, 2012 | 106 | 2012 |
| New placement prediction and mitigation techniques for local routing congestion T Taghavi, Z Li, C Alpert, GJ Nam, A Huber, S Ramji Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on …, 2010 | 102 | 2010 |
| Longest-path selection for delay test under process variation X Lu, Z Li, W Qiu, DMH Walker, W Shi Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2005 | 101 | 2005 |
| Fast algorithms for slew constrained minimum cost buffering S Hu, CJ Alpert, J Hu, S Karandikar, Z Li, W Shi, CN Sze Proceedings of the 43rd annual Design Automation Conference, 308-313, 2006 | 99 | 2006 |
| GLARE: Global and local wiring aware routability evaluation Y Wei, C Sze, N Viswanathan, Z Li, CJ Alpert, L Reddy, AD Huber, ... Proceedings of the 49th Annual Design Automation Conference, 768-773, 2012 | 93 | 2012 |
| Timing refinement re-routing MA Kazda, Z Li, GJ Nam, Y Zhou US Patent 8,635,577, 2014 | 91 | 2014 |
| What makes a design difficult to route CJ Alpert, Z Li, MD Moffitt, GJ Nam, JA Roy, G Tellez Proceedings of the 19th international symposium on Physical design, 7-12, 2010 | 81 | 2010 |
| Techniques for fast physical synthesis CJ Alpert, SK Karandikar, Z Li, GJ Nam, ST Quay, H Ren, CN Sze, ... Proceedings of the IEEE 95 (3), 573-599, 2007 | 80 | 2007 |
| A circuit level fault model for resistive opens and bridges Z Li, X Lu, W Qiu, W Shi, DMH Walker Proceedings. 21st VLSI Test Symposium, 2003., 379-384, 2003 | 80 | 2003 |
| Methodology for standard cell compliance and detailed placement for triple patterning lithography B Yu, X Xu, JR Gao, Y Lin, Z Li, CJ Alpert, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 76 | 2015 |
| Solidification behavior and grain morphology of laser additive manufacturing titanium alloys YY Zhu, HB Tang, Z Li, C Xu, B He Journal of Alloys and Compounds 777, 712-716, 2019 | 67 | 2019 |
| ICCAD-2013 CAD contest in mask optimization and benchmark suite S Banerjee, Z Li, SR Nassif 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 271-274, 2013 | 66 | 2013 |
| MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes Y Lin, B Yu, X Xu, JR Gao, N Viswanathan, WH Liu, Z Li, CJ Alpert, ... 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 59 | 2016 |
| Fast interconnect synthesis with layer assignment Z Li, CJ Alpert, S Hu, T Muhmud, ST Quay, PG Villarrubia Proceedings of the 2008 international symposium on Physical design, 71-77, 2008 | 56* | 2008 |
| RUMBLE: An incremental timing-driven physical-synthesis optimization algorithm DA Papa, T Luo, MD Moffitt, CN Sze, Z Li, GJ Nam, CJ Alpert, IL Markov Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2008 | 51 | 2008 |
| Physical synthesis with clock-network optimization for large systems on chips D Papa, C Alpert, C Sze, Z Li, N Viswanathan, GJ Nam, I Markov IEEE Micro 31 (4), 51-62, 2011 | 49 | 2011 |
| ITOP: Integrating timing optimization within placement N Viswanathan, GJ Nam, JA Roy, Z Li, CJ Alpert, S Ramji, C Chu Proceedings of the 19th international symposium on Physical design, 83-90, 2010 | 49* | 2010 |
Chuck AlpertSenior Software Architect, Cadence Design SystemsVerified email at cadence.com
