| SALSA: Systematic logic synthesis of approximate circuits S Venkataramani, A Sabne, V Kozhikkottu, K Roy, A Raghunathan Proceedings of the 49th Annual Design Automation Conference, 796-801, 2012 | 392 | 2012 |
| TapeCache: A high density, energy efficient cache based on domain wall memory R Venkatesan, V Kozhikkottu, C Augustine, A Raychowdhury, K Roy, ... Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 171 | 2012 |
| Cache design with domain wall memory R Venkatesan, VJ Kozhikkottu, M Sharad, C Augustine, A Raychowdhury, ... IEEE Transactions on Computers 65 (4), 1010-1024, 2015 | 43 | 2015 |
| Logic synthesis of approximate circuits S Venkataramani, VJ Kozhikkottu, A Sabne, K Roy, A Raghunathan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 17 | 2019 |
| VESPA: Variability emulation for System-on-Chip performance analysis VJ Kozhikkottu, R Venkatesan, A Raghunathan, S Dey 2011 Design, Automation & Test in Europe, 1-6, 2011 | 10 | 2011 |
| Variation aware cache partitioning for multithreaded programs V Kozhikkottu, A Pan, V Pai, S Dey, A Raghunathan Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 9 | 2014 |
| Recovery-based design for variation-tolerant SoCs V Kozhikkottu, S Dey, A Raghunathan Proceedings of the 49th Annual Design Automation Conference, 826-833, 2012 | 9 | 2012 |
| Energy efficient read/write support for a protected memory V Kozhikkottu, D Somasekhar, YM Kim, SP Park US Patent App. 15/089,340, 2017 | 8 | 2017 |
| Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality data KW Kwon, V Kozhikkottu, SP Park, A More, WP Griffin, R Pawlowski, ... US Patent App. 15/477,072, 2018 | 6 | 2018 |
| Minimal aliasing single-error-correction codes for dram reliability improvement SI Pae, V Kozhikkottu, D Somasekar, W Wu, SG Ramasubramanian, ... IEEE Access 9, 29862-29869, 2021 | 5 | 2021 |
| Memory controller that forces prefetches in response to a present row address change timing constraint A Ranjan, V Kozhikkottu US Patent 10,268,585, 2019 | 4 | 2019 |
| Variation tolerant design of a vector processor for recognition, mining and synthesis V Kozhikkottu, S Venkataramani, S Dey, A Raghunathan Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 4 | 2014 |
| Low latency statistical data bus inversion for energy reduction V Kozhikkottu, SG Ramasubramanian, KW Kwon, D Somasekhar US Patent 10,853,300, 2020 | 3 | 2020 |
| Address range based in-band memory error-correcting code protection module with syndrome buffer AA Radjai, N Aboulenein, SL Geiger, SA Jadhav, BJ Kapadia, ... US Patent App. 16/504,199, 2019 | 3 | 2019 |
| Low-overhead mechanism to detect address faults in ECC-protected memories KW Kwon, V Kozhikkottu, D Somasekhar US Patent 10,319,461, 2019 | 3 | 2019 |
| Increasing read pending queue capacity to increase memory bandwidth G Koo, V Kozhikkottu, SG Ramasubramanian, CB Wilkerson US Patent App. 15/395,615, 2018 | 3 | 2018 |
| Memory device with local cache array JW Lee, V Kozhikkottu, KS Bains, H Alameer US Patent 11,144,466, 2021 | 1 | 2021 |
| Two-level main memory hierarchy management SP Muralidhara, AR Alameldeen, R Agarwal, V Kozhikkottu US Patent App. 17/214,818, 2021 | 1 | 2021 |
| Fast search of error correction code (ECC) protected data in a memory W Wu, D Somasekhar, J Stephan, AK Radhakrishnan, V Kozhikkottu US Patent 10,884,853, 2021 | 1 | 2021 |
| Minimal aliasing bit-error correction code D Somasekhar, W Wu, SG Ramasubramanian, V Kozhikkottu, M Dadual US Patent 10,860,419, 2020 | 1 | 2020 |
Anand RaghunathanProfessor of Electrical and Computer Engineering, Purdue UniversityVerified email at purdue.edu
