Yu-Hsin Chen
Yu-Hsin Chen
Lead AI Architect at EnCharge AI
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Efficient processing of deep neural networks: A tutorial and survey
V Sze, YH Chen, TJ Yang, JS Emer
Proceedings of the IEEE 105 (12), 2295-2329, 2017
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
YH Chen, T Krishna, J Emer, V Sze
IEEE Journal of Solid-State Circuits (JSSC) 52 (1), 127-138, 2016
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
YH Chen, J Emer, V Sze
The 43rd International Symposium on Computer Architecture (ISCA), 2016
Single-chip microprocessor that communicates directly using light
C Sun, MT Wade, Y Lee, JS Orcutt, L Alloatti, MS Georgas, AS Waterman, ...
Nature 528 (7583), 534-538, 2015
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices
YH Chen, TJ Yang, J Emer, V Sze
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2019
Designing energy-efficient convolutional neural networks using energy-aware pruning
TJ Yang, YH Chen, V Sze
Proceedings of the IEEE conference on computer vision and pattern …, 2017
Hardware for Machine Learning: Challenges and Opportunities
V Sze, YH Chen, JS Emer, A Suleiman, Z Zhang
arXiv preprint arXiv:1612.07625, 2016
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ...
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019
Using dataflow to optimize energy efficiency of deep neural network accelerators
YH Chen, J Emer, V Sze
IEEE Micro 37 (3), 12-21, 2017
A method to estimate the energy consumption of deep neural networks
TJ Yang, YH Chen, J Emer, V Sze
2017 51st asilomar conference on signals, systems, and computers, 1916-1920, 2017
Hardware architectures for deep neural networks
J Emer, V Sze, YH Chen, TJ Yang
CICS/MTL Tutorial, Mar 27, 258, 2017
Heterogeneous dataflow accelerators for multi-DNN workloads
H Kwon, L Lai, M Pellauer, T Krishna, YH Chen, V Chandra
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
Towards closing the energy gap between HOG and CNN features for embedded vision
A Suleiman, YH Chen, J Emer, V Sze
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
A monolithically-integrated chip-to-chip optical link in bulk CMOS
C Sun, M Georgas, J Orcutt, B Moss, YH Chen, J Shainline, M Wade, ...
IEEE Journal of Solid-State Circuits 50 (4), 828-844, 2015
Understanding the Limitations of Existing Energy-Efficient Design Approaches for Deep Neural Networks
YH Chen, TJ Yang, J Emer, V Sze
SysML, 2018
How to evaluate deep neural network processors: Tops/w (alone) considered harmful
V Sze, YH Chen, TJ Yang, JS Emer
IEEE Solid-State Circuits Magazine 12 (3), 28-41, 2020
Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform
KT Settaluri, S Lin, S Moazeni, E Timurdogan, C Sun, M Moresco, Z Su, ...
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
A 1.23 pJ/b 2.5 Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOI
BR Moss, C Sun, M Georgas, J Shainline, JS Orcutt, JC Leu, M Wade, ...
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
Tutorial on hardware architectures for deep neural networks
J Emer, V Sze, YH Chen
IEEE/ACM International Symposium on Microarchitecture (MICRO-49), 2016
A deeply pipelined CABAC decoder for HEVC supporting level 6.2 high-tier applications
YH Chen, V Sze
IEEE Transactions on Circuits and Systems for Video Technology 25 (5), 856-868, 2014
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