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Kunhyuk Kang
Kunhyuk Kang
Seoul National University, Purdue University, Intel Corporation, Qualcomm Inc., Samsung Electronics
Verified email at qti.qualcomm.com
Title
Cited by
Cited by
Year
Impact of NBTI on the temporal performance degradation of digital circuits
BC Paul, K Kang, H Kufluoglu, MA Alam, K Roy
IEEE Electron Device Letters 26 (8), 560-562, 2005
3682005
Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits
BC Paul, K Kang, H Kufluoglu, MA Alam, K Roy
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
2072006
Impact of negative-bias temperature instability in nanoscale SRAM array: Modeling and analysis
K Kang, H Kufluoglu, K Roy, MA Alam
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
1992007
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance
K Kang, SP Park, K Roy, MA Alam
2007 IEEE/ACM international conference on computer-aided design, 730-734, 2007
1212007
NBTI induced performance degradation in logic and memory circuits: How effectively can we approach a reliability solution?
K Kang, S Gangwal, SP Park, R Kaushik
2008 Asia and South Pacific Design Automation Conference, 726-731, 2008
1172008
Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuits
BC Paul, K Kang, H Kufluoglu, MA Alam, K Roy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
1022007
On-chip variability sensor using phase-locked loop for detecting and correcting parametric timing failures
K Kang, SP Park, K Kim, K Roy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (2), 270-280, 2009
872009
Efficient transistor-level sizing technique under temporal performance degradation due to NBTI
K Kang, H Kufluoglu, MA Alam, K Roy
2006 International Conference on Computer Design, 216-221, 2006
852006
Reliability implications of bias-temperature instability in digital ICs
SP Park, K Kang, K Roy
IEEE Design & Test of Computers 26 (6), 8-17, 2009
812009
Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ
K Kang, MA Alam, K Roy
2007 IEEE International Test Conference, 1-10, 2007
812007
Characterization and estimation of circuit reliability degradation under NBTI using on-line IDDQ measurement
K Kang, K Kim, AE Islam, MA Alam, K Roy
Proceedings of the 44th annual Design Automation Conference, 358-363, 2007
702007
Statistical timing analysis using levelized covariance propagation
K Kang, BC Paul, K Roy
Design, Automation and Test in Europe, 764-769, 2005
682005
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring
S Mukhopadhyay, K Kang, H Mahmoodi, K Roy
IEEE International Conference on Test, 2005., 10 pp.-1135, 2005
622005
Accurate estimation and modeling of total chip leakage considering inter-& intra-die process variations
A Agarwal, K Kang, K Roy
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
442005
Reliability-and process-variation aware design of vlsi circuits
M Alam, K Kang, BC Paul, K Roy
2007 14th International Symposium on the Physical and Failure Analysis of …, 2007
402007
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters
K Kang, BC Paul, K Roy
ACM Transactions on Design Automation of Electronic Systems (TODAES) 11 (4 …, 2006
342006
Variation resilient low-power circuit design methodology using on-chip phase locked loop
K Kang, K Kim, K Roy
Proceedings of the 44th annual Design Automation Conference, 934-939, 2007
302007
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling
IJ Chang, K Kang, S Mukhopadhyay, CH Kim, K Roy
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 …, 2005
302005
Device-Aware Yield-Centric Dual- Design Under Parameter Variations in Nanoscale Technologies
A Agarwal, K Kang, S Bhunia, JD Gallagher, K Roy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (6), 660-671, 2007
262007
Variation estimation and compensation technique in scaled LTPS TFT circuits for low-power low-cost applications
J Li, K Kang, K Roy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
242008
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Articles 1–20