| Programmable nanowire circuits for nanoprocessors H Yan, HS Choe, SW Nam, Y Hu, S Das, JF Klemic, JC Ellenbogen, ... Nature 470 (7333), 240-244, 2011 | 600 | 2011 |
| Wiring requirement and three-dimensional integration technology for field programmable gate arrays A Rahman, S Das, AP Chandrakasan, R Reif IEEE Transactions on very large scale integration (VLSI) systems 11 (1), 44-54, 2003 | 245 | 2003 |
| Technology, performance, and computer-aided design of three-dimensional integrated circuits S Das, A Fan, KN Chen, CS Tan, N Checka, R Reif Proceedings of the 2004 international symposium on Physical design, 108-115, 2004 | 208 | 2004 |
| Fabrication technologies for three-dimensional integrated circuits R Reif, A Fan, KN Chen, S Das Proceedings International Symposium on Quality Electronic Design, 33-37, 2002 | 168 | 2002 |
| Design tools for 3-D integrated circuits S Das, A Chandrakasan, R Reif Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003 | 147 | 2003 |
| Design automation and analysis of three-dimensional integrated circuits S Das Massachusetts Institute of Technology, 2004 | 145 | 2004 |
| Three-dimensional integrated circuits: performance, design methodology, and CAD tools S Das, A Chandrakasan, R Reif IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 13-18, 2003 | 115 | 2003 |
| Nanowire nanocomputer as a finite-state machine J Yao, H Yan, S Das, JF Klemic, JC Ellenbogen, CM Lieber Proceedings of the National Academy of Sciences 111 (7), 2431-2435, 2014 | 93 | 2014 |
| Timing, energy, and thermal performance of three-dimensional integrated circuits S Das, A Chandrakasan, R Reif Proceedings of the 14th ACM Great Lakes symposium on VLSI, 338-343, 2004 | 83 | 2004 |
| Calibration of Rent's rule models for three-dimensional integrated circuits S Das, AP Chandrakasan, R Reif IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (4), 359-366, 2004 | 65 | 2004 |
| Designs for ultra-tiny, special-purpose nanoelectronic circuits S Das, AJ Gates, HA Abdu, GS Rose, CA Picconatto, JC Ellenbogen IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2528-2540, 2007 | 64 | 2007 |
| Switching-time analysis of binary-oxide memristors via a nonlinear model N Hashem, S Das Applied Physics Letters 100 (26), 2012 | 50 | 2012 |
| 3-D interconnects using Cu wafer bonding: Technology and applications R Reif, CS Tan, A Fan, KN Chen, S Das, N Checka Advanced Metallization Conference, San Diego, 2002 | 34 | 2002 |
| Architectures and simulations for nanoprocessor systems integrated on the molecular scale S Das, G Rose, MM Ziegler, CA Picconatto, JC Ellenbogen Introducing Molecular Electronics, 479-512, 2005 | 32 | 2005 |
| Wiring requirement and three-dimensional integration of field-programmable gate arrays A Rahman, S Das, A Chandraksan, R Reif Proceedings of the 2001 international workshop on System-level interconnect …, 2001 | 27 | 2001 |
| SPICE-compatible compact model for graphene field-effect transistors MB Henry, S Das 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2521-2524, 2012 | 26 | 2012 |
| Multi-layer integrated semiconductor structure R Reif, S Das, A Fan US Patent App. 10/655,854, 2004 | 25 | 2004 |
| International Roadmap of Devices and Systems 2017 Edition: Beyond CMOS chapter. S Agarwal, G Burr, A Chen, S Das, E Debenedictis, MP Frank, P Franzon, ... Sandia National Lab.(SNL-NM), Albuquerque, NM (United States), 2018 | 16 | 2018 |
| Performance simulation and analysis of a CMOS/nano hybrid nanoprocessor system AC Cabe, S Das Nanotechnology 20 (16), 165203, 2009 | 12 | 2009 |
| System-level design and simulation of nanomemories and nanoprocessors S Das, CA Picconatto, GS Rose, MM Ziegler, JC Ellenbogen Nano and Molecular Electronics Handbook, 5-1-5-39, 2018 | 7 | 2018 |
