Seznec Andre

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Francois BodinUniversité de Rennes 1Verified email at irisa.fr
Erven RohouUniv Rennes, Inria, CNRS, IRISAVerified email at inria.fr
Arthur PeraisCNRSVerified email at univ-grenoble-alpes.fr
Yiannakis (Yanos) SazeidesUniversity of CyprusVerified email at cs.ucy.ac.cy
Michael O'BoyleProfessor of Computer Science, University of EdinburghVerified email at inf.ed.ac.uk
Pascal SainratProfessor in Computer Science, Traces-IRIT, Université Paul Sabatier - Toulouse IIIVerified email at irit.fr
Hans VandierendonckQueen's University Belfast, ProfessorVerified email at qub.ac.uk
Richard UhligUniversity of Michigan, Intel CorporationVerified email at intel.com
Julio Hernandez-CastroProfessor of Computer Security, University of KentVerified email at kent.ac.uk
Joel EmerProfessor of the Practice, MIT - Sr. Distinguished Research Scientist, NvidiaVerified email at csail.mit.edu
William JALBYProfessor of Computer UVSQ CTO ECRVerified email at uvsq.fr
Nicolas SendrierInriaVerified email at inria.fr
Jose Sierra (Camara)Northeastern UniverstiyVerified email at neu.edu
David A. WoodUniversity of Wisconsin, MadisonVerified email at cs.wisc.edu
Somayeh SardashtiUniversity of Wisconsin-MadisonVerified email at cs.wisc.edu
Henri-Pierre CharlesCEAVerified email at cea.fr
Michel BARRETEAUThales Research & Technology FranceVerified email at thalesgroup.com
Venkata KrishnanNvidiaVerified email at nvidia.com
Biswabandan PandaIIT BombayVerified email at iitb.ac.in
Rizos SakellariouUniversity of Manchester, Department of Computer ScienceVerified email at cs.man.ac.uk

Seznec Andre

INRIA/IRISA

Verified email at inria.fr - Homepage

Computer Architecture


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A case for two-way skewed-associative caches A Seznec ACM SIGARCH computer architecture news 21 (2), 169-178, 1993	451	1993
A case for (partially) tagged geometric history length branch prediction A Seznec, P Michaud The Journal of Instruction-Level Parallelism 8, 23, 2006	323	2006
Design tradeoffs for the Alpha EV8 conditional branch predictor A Seznec, S Felix, V Krishnan, Y Sazeides ACM SIGARCH Computer Architecture News 30 (2), 295-306, 2002	282	2002
Trading conflict and capacity aliasing in conditional branch predictors P Michaud, A Seznec, R Uhlig Proceedings of the 24th annual international symposium on Computer …, 1997	279	1997
A 256 kbits l-tage branch predictor A Seznec Journal of Instruction-Level Parallelism (JILP) Special Issue: The Second …, 2007	187	2007
Analysis of the o-geometric history length branch predictor A Seznec 32nd International Symposium on Computer Architecture (ISCA'05), 394-405, 2005	177	2005
Decoupled sectored caches: conciliating low tag implementation cost A Seznec Proceedings of the 21st annual international symposium on Computer …, 1994	175	1994
Zero-content augmented caches J Dusser, T Piquet, A Seznec Proceedings of the 23rd international conference on Supercomputing, 46-55, 2009	167	2009
A new case for the tage branch predictor A Seznec Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011	161	2011
Performance implications of single thread migration on a chip multi-core T Constantinou, Y Sazeides, P Michaud, D Fetis, A Seznec ACM SIGARCH Computer Architecture News 33 (4), 80-91, 2005	160	2005
Multiple-block ahead branch predictors A Seznec, S Jourdan, P Sainrat, P Michaud ACM SIGPLAN Notices 31 (9), 116-127, 1996	160	1996
Improving cache behavior of dynamically allocated data structures DN Truong, F Bodin, A Seznec Proceedings. 1998 International Conference on Parallel Architectures and …, 1998	155	1998
Tarantula: a vector extension to the alpha architecture R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ... ACM SIGARCH Computer Architecture News 30 (2), 281-292, 2002	151	2002
Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream T Lafage, A Seznec Workload characterization of emerging computer applications, 145-163, 2001	145	2001
Data-flow prescheduling for large instruction windows in out-of-order processors P Michaud, A Seznec Proceedings HPCA Seventh International Symposium on High-Performance …, 2001	138	2001
The strict avalanche criterion randomness test JCH Castro, JM Sierra, A Seznec, A Izquierdo, A Ribagorda Mathematics and Computers in Simulation 68 (1), 1-7, 2005	131	2005
Performance upper bound analysis and optimization of SGEMM on Fermi and Kepler GPUs J Lai, A Seznec Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation …, 2013	127	2013
Practical and secure pcm systems by online detection of malicious write streams MK Qureshi, A Seznec, LA Lastras, MM Franceschini 2011 IEEE 17th International symposium on high performance computer …, 2011	119	2011
Skewed-associative caches A Seznec, F Bodin PARLE'93 Parallel Architectures and Languages Europe: 5th International …, 1993	103	1993
Prediction-based superpage-friendly TLB designs MM Papadopoulou, X Tong, A Seznec, A Moshovos 2015 IEEE 21st International Symposium on High Performance Computer …, 2015	96	2015

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