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Ricardo Gómez Gómez
Ricardo Gómez Gómez
Program Manager, Intel Corporation
Verified email at intel.com
Title
Cited by
Cited by
Year
Design Methodology with Body Bias: from Circuit to Engineering
R Gomez, C Dutto, V Huard, S Clerc, E Bano, P Flatresse
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2017
52017
Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology
R Gomez, E Bano, S Clerc
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2019
42019
A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI
RG Gomez, E Bano, A Cathelin, S Clerc
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
22020
Timing-Based Closed Loop Compensation
RG Gomez, S Clerc
The Fourth Terminal: Benefits of Body-Biasing Techniques for FDSOI Circuits …, 2020
12020
Memory Power Management for Java Processors Using Heap Partitioning and Power Gating
R Gomez, F Gruian, L Liu
Proceedings of the 14th International Workshop on Java Technologies for Real …, 2016
12016
Device, method and system of error detection and correction in multiple devices
RG GOMEZ, S Clerc
US Patent 11,385,288, 2022
2022
Method, system and device to test a plurality of devices by comparing test results of test chains of the plurality of devices
RG GOMEZ
US Patent 11,353,508, 2022
2022
Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies
S Clerc, KJ Dhori, RM Wilson, R Goel, S Marchal, F Pourchon, C Dutto, ...
ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021
2021
Digital circuit monitoring device
RG GOMEZ, S Clerc
US Patent App. 17/189,984, 2021
2021
A Review of Circuit Monitoring in 28nm FDSOI and 40nm Bulk CMOS Technologies
S Clerc, D Kedar Janardan, R Wilson, R Goel, S Marchal, F Pourchon, ...
2021 IEEE European Solid-State Circuits Conference (ESSCIRC), 2021
2021
(Invited Talk) Combined AVS-ABB and Circuit Monitoring for Reliable and Energy Efficient SoC Design
R Gomez Gomez
2020 IEEE European Solid-State Circuits Conference (ESSCIRC), 2020
2020
Body-Bias for Digital Designs
S Clerc, RG Gomez
The Fourth Terminal: Benefits of Body-Biasing Techniques for FDSOI Circuits …, 2020
2020
Open Loop Compensation
S Clerc, RG Gomez
The Fourth Terminal: Benefits of Body-Biasing Techniques for FDSOI Circuits …, 2020
2020
Compensation and Regulation Solutions’ Synthesis
RG Gomez
The Fourth Terminal: Benefits of Body-Biasing Techniques for FDSOI Circuits …, 2020
2020
Memory Energy Optimizations for IoT Processors
R Gómez
2016
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