| Semiconductor device extractor for electrostatic discharge and latch-up applications S Ramaswamy, S Sinha, G Kadamati, R Gharpurey US Patent 6,553,542, 2003 | 52 | 2003 |
| An automated tool for detecting ESD design errors S Siha, H Swaminathan, G Kadamati, C Duvvury Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1998 …, 1998 | 46 | 1998 |
| Photoluminescence-excitation spectroscopy of porous silicon S Sinha, S Banerjee, BM Arora Physical Review B 49 (8), 5706, 1994 | 40 | 1994 |
| A 65nm C64x+ multi-core DSP platform for communications infrastructure S Agarwala, A Rajagopal, A Hill, M Joshi, S Mullinnix, T Anderson, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 35 | 2007 |
| Integrated circuit design error detector for electrostatic discharge and latch-up applications P Venugopal, S Sinha, S Ramaswamy, C Duvvury, GC Prasad, CS Raghu, ... US Patent 6,493,850, 2002 | 29 | 2002 |
| System and method for modeling an integrated circuit system SN Kiel, S Sinha, GE Howard US Patent 7,281,223, 2007 | 26 | 2007 |
| Method for estimating substrate noise in mixed signal integrated circuits S Sinha, B Ghosh, RN Srinivasa, SN Kiel US Patent 6,986,113, 2006 | 23 | 2006 |
| 0.8-eV photoluminescence band in Al x Ga 1− x As S Sinha, AK Srivastava, S Banerjee, BM Arora Physical Review B 44 (19), 10941, 1991 | 12 | 1991 |
| Photoreflectance and photoluminescence spectroscopy of low‐temperature GaAs grown by molecular‐beam epitaxy S Sinha, BM Arora, S Subramanian Journal of applied physics 79 (1), 427-432, 1996 | 8 | 1996 |
| A photoluminescence and photocapacitance study of GaAs: In and GaAs: Sb layers grown by liquid-phase epitaxy K Mallik, S Dhar, S Sinha Semiconductor science and technology 9 (9), 1649, 1994 | 6 | 1994 |
| Techniques for correlating power distribution network simulations with physical measurements F Cano, K Lavery, S Sinha, T Bandyopadhyay, B McCracken, S Stelmach 2023 IEEE 27th Workshop on Signal and Power Integrity (SPI), 1-4, 2023 | 1 | 2023 |
| Electronic substrate having differential coaxial vias S Sinha, T Bandyopadhyay, MR Kulkarni US Patent App. 18/353,295, 2023 | | 2023 |
| Method of forming package substrate with partially recessed capacitor JM Williamson, S Sinha US Patent 11,804,382, 2023 | | 2023 |
| Electronic substrate having differential coaxial vias S Sinha, T Bandyopadhyay, MR Kulkarni US Patent 11,800,636, 2023 | | 2023 |
| Embedded lid for low cost and improved thermal performance HX Nguyen, JM Wiliamson, AN Verdeflor, S Sinha US Patent App. 17/510,684, 2022 | | 2022 |
| Package substrate with partially recessed capacitor JM Williamson, S Sinha US Patent 11,289,412, 2022 | | 2022 |
| Electronic substrate having differential coaxial vias S Sinha, T Bandyopadhyay, MR Kulkarni US Patent 11,160,163, 2021 | | 2021 |
| Deep dive into DDR3 interface jitter contributors RDM SM Stalin, K Scholz, T Bandyopadhyay, S Moharil, S Sinha IEEE 21st Workshop on Signal and Power Integrity (SPI), 2017, 2017 | | 2017 |
| Signal integrity analysis of serpentine traces in IC packages SS Ashwini Datta, Narahari Datta, Tapobrata Bandyopadhyay Circuits and Systems Conference (DCAS), 2016 IEEE Dallas, 2016 | | 2016 |
| System Co-Design for Low Power, High Performance Multicore DSP Systems SS Tapobrata Bandyopadhyay, Anita Pratti, Bill Taboada, Thomas Krause, Tom ... Electronic Components and Technology Conference (ECTC), 2016 IEEE 66th, 2016 | | 2016 |
Brij Mohan AroraVisiting Professor , Indian Institute of Technology BombayVerified email at ee.iitb.ac.in
