Jason Lowe-Power

Cited by

	All	Since 2017
Citations	1018	813
h-index	13	12
i10-index	14	13

180

135

20142015201620172018201920202021202222 55 100 125 115 109 115 177 168

Public access

View all

9 articles

0 articles

available

not available

Based on funding mandates

Co-authors

Mark D. HillMicrosoft Partner Hardware Architect & University of Wisconsin-Madison Professor EmeritusVerified email at cs.wisc.edu
David A. WoodUniversity of Wisconsin, MadisonVerified email at cs.wisc.edu
Venkatesh AkellaProfessor of Electrical & Computer Engineering, University of California, DavisVerified email at ucdavis.edu
Ayaz AkramUniversity of California, DavisVerified email at ucdavis.edu
Marc OrrGoogleVerified email at cs.wisc.edu
Christopher NittaAssociate Professor of Teaching, University of California, DavisVerified email at ucdavis.edu
Sean PeisertCybersecurity & Privacy R&D Lead, Lawrence Berkeley National Laboratory; Adjunct Professor, UC DavisVerified email at ucdavis.edu
Arkaprava BasuAssociate Professor at Indian Institute of Science (IISc)Verified email at iisc.ac.in
Steven K. ReinhardtMicrosoftVerified email at microsoft.com
Jignesh M. PatelUniversity of WisconsinVerified email at cs.wisc.edu
Matt FarrensUniversity of California, DavisVerified email at cs.ucdavis.edu
Pouya FotouhiUniversity of California at DavisVerified email at ucdavis.edu
S. J. B. YooUniversity of California, Davis; Lawrence Berkeley Laboratory; BellcoreVerified email at ucdavis.edu
Lena E. OlsonGoogleVerified email at google.com
Hongil YoonGoogleVerified email at cs.wisc.edu
Sanjeev TrikaGoogleVerified email at google.com
Sebastian WernerUC DavisVerified email at ucdavis.edu
Mahyar SamaniUniversity of California DavisVerified email at ucdavis.edu
Tony NowatzkiUniversity of California, Los AngelesVerified email at cs.ucla.edu
Zhengrong WangUCLAVerified email at ucla.edu

Jason Lowe-Power

Assistant Professor, University of California, Davis

Verified email at ucdavis.edu - Homepage

Computer architecture


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
gem5-gpu: A heterogeneous cpu-gpu simulator J Power, J Hestness, M Orr, M Hill, D Wood IEEE, 2014	288	2014
Heterogeneous system coherence for integrated CPU-GPU systems J Power, A Basu, J Gu, S Puthoor, BM Beckmann, MD Hill, SK Reinhardt, ... 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013	181	2013
Supporting x86-64 address translation for 100s of GPU lanes J Power, MD Hill, D Wood High Performance Computer Architecture (HPCA), 2014 IEEE 20th International …, 2014	170	2014
The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020	95	2020
Border control: Sandboxing accelerators LE Olson, J Power, MD Hill, DA Wood 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture …, 2015	68	2015
Autotm: Automatic tensor movement in heterogeneous memory systems using integer linear programming M Hildebrand, J Khan, S Trika, J Lowe-Power, V Akella Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020	32	2020
Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries J Power, Y Li, MD Hill, JM Patel, DA Wood Proceedings of the 11th International Workshop on Data Management on New …, 2015	29	2015
Filtering translation bandwidth with virtual caching H Yoon, J Lowe-Power, GS Sohi Proceedings of the Twenty-Third International Conference on Architectural …, 2018	23	2018
Enabling scalable chiplet-based uniform memory architectures with silicon photonics P Fotouhi, S Werner, J Lowe-Power, SJB Yoo Proceedings of the International Symposium on Memory Systems, 222-334, 2019	18	2019
Implications of emerging 3D GPU architecture on the scan primitive J Power, Y Li, MD Hill, JM Patel, DA Wood ACM SIGMOD Record 44 (1), 18-23, 2015	15	2015
Stream floating: Enabling proactive and decentralized cache optimizations Z Wang, J Weng, J Lowe-Power, J Gaur, T Nowatzki 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021	14	2021
The Davis In-Order (DINO) CPU: A Teaching-Focused RISC-V CPU Design J Lowe-Power, C Nitta Proceedings of the Workshop on Computer Architecture Education, 1-8, 2019	14	2019
Position Paper: A case for exposing extra-architectural state in the ISA J Lowe-Power, V Akella, MK Farrens, ST King, CJ Nitta Proceedings of the 7th International Workshop on Hardware and Architectural …, 2018	13	2018
Performance analysis of scientific computing workloads on general purpose TEEs A Akram, A Giannakou, V Akella, J Lowe-Power, S Peisert 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2021	10	2021
Performance analysis of scientific computing workloads on trusted execution environments A Akram, A Giannakou, V Akella, J Lowe-Power, S Peisert arXiv preprint arXiv:2010.13216, 2020	9	2020
When to use 3d die-stacked memory for bandwidth-constrained big data workloads J Lowe-Power, MD Hill, DA Wood arXiv preprint arXiv:1608.07485, 2016	8*	2016
Enabling design space exploration for risc-v secure compute environments A Akram, V Akella, S Peisert, J Lowe-Power	7	2021
On Heterogeneous Compute and Memory Systems J Lowe-Power The University of Wisconsin-Madison, 2017	7	2017
A case against hardware managed dram caches for nvram based systems M Hildebrand, JT Angeles, J Lowe-Power, V Akella 2021 IEEE International Symposium on Performance Analysis of Systems and …, 2021	5	2021
Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP K Straube, J Lowe-Power, C Nitta, M Farrens, V Akella 2018 IEEE 25th International Conference on High Performance Computing (HiPC …, 2018	4	2018

The system can't perform the operation now. Try again later.

Articles 1–20

Citations per year

Duplicate citations

Merged citations

Add co-authorsCo-authors

Follow

Cited by

Co-authors