| gem5-gpu: A heterogeneous cpu-gpu simulator J Power, J Hestness, M Orr, M Hill, D Wood IEEE, 2014 | 231 | 2014 |
| Heterogeneous system coherence for integrated CPU-GPU systems J Power, A Basu, J Gu, S Puthoor, BM Beckmann, MD Hill, SK Reinhardt, ... 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013 | 149 | 2013 |
| Supporting x86-64 address translation for 100s of GPU lanes J Power, MD Hill, D Wood High Performance Computer Architecture (HPCA), 2014 IEEE 20th International …, 2014 | 148 | 2014 |
| Border control: Sandboxing accelerators LE Olson, J Power, MD Hill, DA Wood 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture …, 2015 | 50 | 2015 |
| Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries J Power, Y Li, MD Hill, JM Patel, DA Wood Proceedings of the 11th International Workshop on Data Management on New …, 2015 | 24 | 2015 |
| Filtering translation bandwidth with virtual caching H Yoon, J Lowe-Power, GS Sohi Proceedings of the Twenty-Third International Conference on Architectural …, 2018 | 15 | 2018 |
| Implications of emerging 3D GPU architecture on the scan primitive J Power, Y Li, MD Hill, JM Patel, DA Wood ACM SIGMOD Record 44 (1), 18-23, 2015 | 14 | 2015 |
| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 12 | 2020 |
| AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming M Hildebrand, J Khan, S Trika, J Lowe-Power, V Akella Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 11 | 2020 |
| Position Paper: A case for exposing extra-architectural state in the ISA J Lowe-Power, V Akella, MK Farrens, ST King, CJ Nitta Proceedings of the 7th International Workshop on Hardware and Architectural …, 2018 | 8* | 2018 |
| When to use 3d die-stacked memory for bandwidth-constrained big data workloads J Lowe-Power, MD Hill, DA Wood arXiv preprint arXiv:1608.07485, 2016 | 8 | 2016 |
| On Heterogeneous Compute and Memory Systems J Lowe-Power University of Wisconsin--Madison, 2017 | 5 | 2017 |
| The Davis In-Order (DINO) CPU: A Teaching-focused RISC-V CPU Design J Lowe-Power, C Nitta Proceedings of the Workshop on Computer Architecture Education, 1-8, 2019 | 3 | 2019 |
| Enabling scalable chiplet-based uniform memory architectures with silicon photonics P Fotouhi, S Werner, J Lowe-Power, SJB Yoo Proceedings of the International Symposium on Memory Systems, 222-334, 2019 | 2 | 2019 |
| Reducing gpu address translation overhead with virtual caching H Yoon, J Lowe-Power, GS Sohi | 2 | 2016 |
| Performance Analysis of Scientific Computing Workloads on Trusted Execution Environments A Akram, A Giannakou, V Akella, J Lowe-Power, S Peisert arXiv preprint arXiv:2010.13216, 2020 | 1 | 2020 |
| Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP K Straube, J Lowe-Power, C Nitta, M Farrens, V Akella 2018 IEEE 25th International Conference on High Performance Computing (HiPC …, 2018 | 1 | 2018 |
| A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems M Hildebrand, JT Angeles, J Lowe-Power, V Akella 2021 IEEE International Symposium on Performance Analysis of Systems and …, 2021 | | 2021 |
| Enabling Reproducible and Agile Full-System Simulation BR Bruce, A Akram, H Nguyen, K Roarty, M Samani, M Friborz, T Reddy, ... 2021 IEEE International Symposium on Performance Analysis of Systems and …, 2021 | | 2021 |
| Stream Floating: Enabling Proactive and Decentralized Cache Optimizations Z Wang, J Weng, J Lowe-Power, J Gaur, T Nowatzki 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | | 2021 |
Mark D. HillProfessor of Computer Sciences and ECE, University of Wisconsin-MadisonVerified email at cs.wisc.edu
