| gem5-gpu: A heterogeneous cpu-gpu simulator J Power, J Hestness, M Orr, M Hill, D Wood IEEE, 2014 | 243 | 2014 |
| Heterogeneous system coherence for integrated CPU-GPU systems J Power, A Basu, J Gu, S Puthoor, BM Beckmann, MD Hill, SK Reinhardt, ... 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013 | 158 | 2013 |
| Supporting x86-64 address translation for 100s of GPU lanes J Power, MD Hill, D Wood High Performance Computer Architecture (HPCA), 2014 IEEE 20th International …, 2014 | 151 | 2014 |
| Border control: Sandboxing accelerators LE Olson, J Power, MD Hill, DA Wood 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture …, 2015 | 55 | 2015 |
| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 26 | 2020 |
| Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries J Power, Y Li, MD Hill, JM Patel, DA Wood Proceedings of the 11th International Workshop on Data Management on New …, 2015 | 25 | 2015 |
| Implications of emerging 3D GPU architecture on the scan primitive J Power, Y Li, MD Hill, JM Patel, DA Wood ACM SIGMOD Record 44 (1), 18-23, 2015 | 16 | 2015 |
| Filtering translation bandwidth with virtual caching H Yoon, J Lowe-Power, GS Sohi Proceedings of the Twenty-Third International Conference on Architectural …, 2018 | 15 | 2018 |
| Autotm: Automatic tensor movement in heterogeneous memory systems using integer linear programming M Hildebrand, J Khan, S Trika, J Lowe-Power, V Akella Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 13 | 2020 |
| Position Paper: A case for exposing extra-architectural state in the ISA J Lowe-Power, V Akella, MK Farrens, ST King, CJ Nitta Proceedings of the 7th International Workshop on Hardware and Architectural …, 2018 | 9* | 2018 |
| When to use 3d die-stacked memory for bandwidth-constrained big data workloads J Lowe-Power, MD Hill, DA Wood arXiv preprint arXiv:1608.07485, 2016 | 8* | 2016 |
| The Davis In-Order (DINO) CPU: A Teaching-Focused RISC-V CPU Design J Lowe-Power, C Nitta Proceedings of the Workshop on Computer Architecture Education, 1-8, 2019 | 6 | 2019 |
| On Heterogeneous Compute and Memory Systems J Lowe-Power The University of Wisconsin-Madison, 2017 | 5 | 2017 |
| Performance analysis of scientific computing workloads on trusted execution environments A Akram, A Giannakou, V Akella, J Lowe-Power, S Peisert arXiv preprint arXiv:2010.13216, 2020 | 4 | 2020 |
| Enabling scalable chiplet-based uniform memory architectures with silicon photonics P Fotouhi, S Werner, J Lowe-Power, SJB Yoo Proceedings of the International Symposium on Memory Systems, 222-334, 2019 | 4 | 2019 |
| Enabling design space exploration for risc-v secure compute environments A Akram, V Akella, S Peisert, J Lowe-Power | 2 | 2021 |
| Performance analysis of scientific computing workloads on general purpose tees A Akram, A Giannakou, V Akella, J Lowe-Power, S Peisert Proceedings of the 35th IEEE International Parallel & Distributed Processing …, 2021 | 2 | 2021 |
| Stream Floating: Enabling Proactive and Decentralized Cache Optimizations Z Wang, J Weng, J Lowe-Power, J Gaur, T Nowatzki 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 2 | 2021 |
| Reducing gpu address translation overhead with virtual caching H Yoon, J Lowe-Power, GS Sohi | 2 | 2016 |
| Enabling Reproducible and Agile Full-System Simulation BR Bruce, A Akram, H Nguyen, K Roarty, M Samani, M Friborz, T Reddy, ... 2021 IEEE International Symposium on Performance Analysis of Systems and …, 2021 | 1 | 2021 |
Mark D. HillMicrosoft Partner Hardware Architect & University of Wisconsin-Madison Professor EmeritusVerified email at cs.wisc.edu
