| Modeling and optimization of fringe capacitance of nanoscale DGMOS devices A Bansal, BC Paul, K Roy IEEE Transactions on Electron Devices 52 (2), 256-262, 2005 | 214 | 2005 |
| An analytical fringe capacitance model for interconnects using conformal mapping A Bansal, BC Paul, K Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 137 | 2006 |
| Device-optimization technique for robust and low-power FinFET SRAM design in nanoscale era A Bansal, S Mukhopadhyay, K Roy IEEE Transactions on Electron Devices 54 (6), 1409-1419, 2007 | 121 | 2007 |
| FinFET SRAM-device and circuit design considerations H Ananthan, A Bansal, K Roy International Symposium on Signals, Circuits and Systems. Proceedings, SCS …, 2004 | 106 | 2004 |
| Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability A Bansal, R Rao, JJ Kim, S Zafar, JH Stathis, CT Chuang Microelectronics reliability 49 (6), 642-649, 2009 | 103 | 2009 |
| Double-gate SOI devices for low-power and high-performance applications K Roy, H Mahmoodi, S Mukhopadhyay, H Ananthan, A Bansal, T Cakici ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 89 | 2005 |
| Analytical subthreshold potential distribution model for gate underlap double-gate MOS transistors A Bansal, K Roy IEEE transactions on electron devices 54 (7), 1793-1798, 2007 | 66 | 2007 |
| Underlap DGMOS for digital-subthreshold operation BC Paul, A Bansal, K Roy IEEE transactions on electron devices 53 (4), 910-913, 2006 | 66 | 2006 |
| Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs H Miki, N Tega, M Yamaoka, DJ Frank, A Bansal, M Kobayashi, K Cheng, ... 2012 International Electron Devices Meeting, 19.1. 1-19.1. 4, 2012 | 64 | 2012 |
| Evaluation methodology for random telegraph noise effects in SRAM arrays M Yamaoka, H Miki, A Bansal, S Wu, DJ Frank, E Leobandung, K Torii 2011 International Electron Devices Meeting, 32.2. 1-32.2. 4, 2011 | 55 | 2011 |
| Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance A Bansal, R Rao, JJ Kim, S Zafar, JH Stathis, CT Chuang 2009 IEEE International Reliability Physics Symposium, 745-749, 2009 | 49 | 2009 |
| Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices A Bansal, BC Paul, K Roy 2004 IEEE International SOI Conference (IEEE Cat. No. 04CH37573), 94-95, 2004 | 49 | 2004 |
| Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits JH Choi, A Bansal, M Meterelliyoz, J Murthy, K Roy Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 48 | 2006 |
| Asymmetric halo CMOSFET to reduce static power dissipation with improved performance A Bansal, K Roy IEEE Transactions on Electron Devices 52 (3), 397-405, 2005 | 48 | 2005 |
| A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices T Cakici, A Bansal, K Roy IEEE international SOI conference, 21-22, 2003 | 45 | 2003 |
| A high density, carbon nanotube capacitor for decoupling applications M Budnik, A Raychowdhury, A Bansal, K Roy Proceedings of the 43rd annual design automation conference, 935-938, 2006 | 39 | 2006 |
| Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors JJ Kim, A Bansal, R Rao, SH Lo, CT Chuang IEEE Electron Device Letters 30 (8), 852-854, 2009 | 34 | 2009 |
| Poly-Si thin-film transistors: An efficient and low-cost option for digital operation J Li, A Bansal, K Roy IEEE transactions on electron devices 54 (11), 2918-2929, 2007 | 31 | 2007 |
| Circuit and physical design of the zEnterprise™ EC12 microprocessor chips and multi-chip module J Warnock, Y Chan, H Harrer, S Carey, G Salem, D Malone, R Puri, ... IEEE Journal of Solid-State Circuits 49 (1), 9-18, 2013 | 30 | 2013 |
| Self-consistent approach to leakage power and temperature estimation to predict thermal runaway in FinFET circuits JH Choi, A Bansal, M Meterelliyoz, J Murthy, K Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 30 | 2007 |
