| Simulation points for SPEC CPU 2006 AA Nair, LK John 2008 IEEE International Conference on Computer Design, 397-403, 2008 | 59 | 2008 |
| A First-Order Mechanistic Model for Architectural Vulnerability Factor AA Nair, S Eyerman, L Eeckhout, LK John The 39th International Symposium on Computer Architecture (ISCA-39) 1, 273-284, 2012 | 54 | 2012 |
| AVF stressmark: Towards an automated methodology for bounding the worst-case vulnerability to soft errors AA Nair, LK John, L Eeckhout 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 125-136, 2010 | 47 | 2010 |
| Predictive Heterogeneity-Aware Application Scheduling for Chip Multiprocessors J Chen, AA Nair, L John IEEE, 2012 | 10 | 2012 |
| Mechanistic modeling of architectural vulnerability factor AA Nair, S Eyerman, J Chen, LK John, L Eeckhout ACM Transactions on Computer Systems (TOCS) 32 (4), 1-32, 2015 | 6 | 2015 |
| Efficient modeling of soft error vulnerability in microprocessors AA Nair | | 2012 |
| Processor in Memory Architecture for MPEG Motion Estimation AA Nair University of California, Irvine, 2006 | | 2006 |
Stijn EyermanResearch Scientist, Intel BelgiumVerified email at intel.com
