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E-San Jang
E-San Jang
Other namesEsan Jang, 장 이산
IMEC, Leuven, Belgium
Verified email at imec.be
Title
Cited by
Cited by
Year
Compact design of low power standard ternary inverter based on OFF-state current mechanism using nano-CMOS technology
S Shin, E Jang, JW Jeong, BG Park, KR Kim
IEEE Transactions on Electron Devices 62 (8), 2396-2403, 2015
562015
A novel ternary multiplier based on ternary CMOS compact model
Y Kang, J Kim, S Kim, S Shin, ES Jang, JW Jeong, KR Kim, S Kang
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), 25-30, 2017
372017
CMOS-compatible ternary device platform for physical synthesis of multi-valued logic circuits
S Shin, E Jang, JW Jeong, KR Kim
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), 284-289, 2017
122017
Ultra-low standby power and static noise-immune standard ternary inverter based on nanoscale ternary CMOS technology
S Shin, JW Jeong, E Jang, KR Kim
2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO), 13-16, 2017
112017
Demonstration of standrad ternary inverter based on CMOS technology
S Shin, E Jang, JW Jeong, KR Kim
2016 IEEE Silicon Nanoelectronics Workshop (SNW), 170-171, 2016
92016
Gate induced drain leakage reduction with analysis of gate fringing field effect on high-κ/metal gate CMOS technology
E Jang, S Shin, JW Jung, KR Kim
Japanese Journal of Applied Physics 54 (6S1), 06FG10, 2015
62015
Ternary digit logic circuit
KR Kim, SH Shin, E San Jang, JW Jeong
US Patent 10,133,550, 2018
52018
Performance Enhancement of Silicon-Based Sub-Terahertz Detector by Highly Localized Plasmonic Wave in Nano-Ring FET
ES Jang, MW Ryu, R Patel, SH Ahn, KJ Han, KR Kim
IEEE Electron Device Letter 42 (12), 1719-1722, 2021
42021
Record-high performance trantenna based on asymmetric nano-ring FET for polarization-independent large-scale/real-time THz imaging
ES Jang, MW Ryu, R Patel, SH Ahn, HJ Jeon, KJ Han, KR Kim
2019 Symposium on VLSI Technology, T160-T161, 2019
42019
Low leakage III-V/Ge CMOS FinFET design for high-performance logic applications with high-k spacer technology
E Jang, S Shin, JW Jeong, KR Kim
Journal of semiconductor technology and science 18 (3), 295-300, 2018
42018
Device optimization on gate oxide and spacer dielectric permittivity for “well-tempered” nanoscale MOSFET
E Jang, S Shin, JW Jung, YJ Jung, KR Kim
2016 IEEE Silicon Nanoelectronics Workshop (SNW), 156-157, 2016
22016
Multiple negative differential resistance device by using the ambipolar behavior of tunneling field effect transistor with fast switching characteristics
JW Jeong, ES Jang, S Shin, KR Kim
Journal of Nanoscience and Nanotechnology 16 (5), 4753-4757, 2016
22016
Standard ternary inverter based on junction leakage-enhanced nanoscale planar CMOS and its variation immunity
S Shin, E Jang, KR Kim
2014 Silicon Nanoelectronics Workshop (SNW), 1-2, 2014
22014
Highly-sensitive plasmonic nano-ring transistor for monolithic terahertz active antenna
MW Ryu, R Patel, E Jang, SH Ahn, HJ Jeon, MS Choe, E Choi, KJ Han, ...
2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO), 17-21, 2017
12017
Active antenna device based on silicon ring field effect transistor array
KR Kim, E San Jang, MW Ryu, SH Ahn
US Patent 11,784,249, 2023
2023
Monolithic field-effect transistor-antenna device for terahertz wave detection with independent performance parameters
KR Kim, MW Ryu, E San Jang, R Patel, SH Ahn
US Patent App. 17/675,628, 2022
2022
Advanced non-quasi-static (NQS) compact model for characterization of non-resonant plasmonic terahertz detector
SH Ahn, MW Ryu, E Jang, HJ Jeon, KR Kim
2017 International Conference on Simulation of Semiconductor Processes and …, 2017
2017
Multi-Valued Logic Based on CMOS Technology
KR Kim, S Shin, E Jang, JW Jung
IEIE, IEICE, The Electrical Engineering/Electronics, Computer …, 2015
2015
A Publication of the Institute of Electronics and Information Engineers
E Jang, S Shin, JW Jeong, KR Kim, M Li, G Shin, J Lee, SM Lee, J Oh, ...
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Articles 1–19