| Inductive fault analysis of MOS integrated circuits JP Shen, W Maly, FJ Ferguson IEEE Design & Test of Computers 2 (6), 13-26, 1985 | 648 | 1985 |
| Realistic fault modeling for VLSI testing W Maly Proceedings of the 24th ACM/IEEE Design Automation Conference, 173-180, 1987 | 309 | 1987 |
| CMOS bridging fault detection TM Storey, W Maly Proceedings. International Test Conference 1990, 842-851, 1990 | 256 | 1990 |
| Test generation for current testing (CMOS ICs) P Nigh, W Maly IEEE Design & Test of Computers 7 (1), 26-38, 1990 | 252 | 1990 |
| Modeling of lithography related yield losses for CAD of VLSI circuits W Maly IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1985 | 250 | 1985 |
| Built-in current testing-feasibility study W Maly, P Nigh 1988 IEEE International Conference on Computer-Aided Design, 340,341,342,343 …, 1988 | 249 | 1988 |
| Stacked 3-dimensional 6T SRAM cell with independent double gate transistors M Weis, A Pfitzner, D Kasprowicz, R Emling, T Fischer, S Henzler, W Maly, ... 2009 IEEE International Conference on IC Design and Technology, 169-172, 2009 | 235 | 2009 |
| Integrated circuit device, system, and method of fabrication WP Maly US Patent App. 12/300,753, 2009 | 220 | 2009 |
| Iddq test: Sensitivity analysis of scaling TW Williams, RH Dennard, R Kapur, MR Mercer, M Maly Proceedings International Test Conference 1996. Test and Design Validity …, 1996 | 204 | 1996 |
| Computer-aided design for VLSI circuit manufacturability W Maly Proceedings of the IEEE 78 (2), 356-392, 1990 | 195 | 1990 |
| VLSI yield prediction and estimation: A unified framework W Maly, AJ Strojwas, SW Director IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1986 | 189 | 1986 |
| Testing oriented analysis of CMOS ICs with opens W Maly, PK Nag, P Nigh [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89 …, 1988 | 186 | 1988 |
| Current signatures [VLSI circuit testing] AE Gattiker, W Maly Proceedings of 14th VLSI Test Symposium, 112-117, 1996 | 183 | 1996 |
| Yield estimation model for VLSI artwork evaluation W Maly, J Deszczka Electronics Letters 6 (19), 226-227, 1983 | 181 | 1983 |
| Interconnect characteristics of 2.5-D system integration scheme Y Deng, WP Maly Proceedings of the 2001 international symposium on Physical design, 171-175, 2001 | 172 | 2001 |
| Current signatures: application AE Gattiker, W Maly Proceedings International Test Conference 1997, 156-165, 1997 | 162 | 1997 |
| Systematic characterization of physical defects for fault analysis of MOS IC cells W Maly, FJ Ferguson, JP Shen Proceedings of the 1984 international test conference on The three faces of …, 1984 | 151 | 1984 |
| Fault modeling for the testing of mixed integrated circuits A Meixner, W Maly 1991, Proceedings. International Test Conference, 564, 1991 | 136 | 1991 |
| VLSI design for manufacturing: yield enhancement SW Director, W Maly, AJ Strojwas Springer Science & Business Media, 2012 | 131 | 2012 |
| Built-in current testing W Maly, M Patyra IEEE Journal of Solid-State Circuits 27 (3), 425-428, 1992 | 119 | 1992 |
Janusz RajskiVice President of Engineering, SiemensVerified email at mentor.com
